Communications: electrical – Digital comparator systems
Patent
1976-04-29
1977-08-23
Fears, Terrell W.
Communications: electrical
Digital comparator systems
340173FF, 307279, G11C 1140
Patent
active
040443434
ABSTRACT:
A non-volatile random access memory system includes a memory array circuit having a plurality of unit non-volatile memory cells arranged in a matrix array. Each unit memory cell includes a flip-flop circuit and two MNOS transistors into which a data in the flip-flop is written and from which the data written therein is transferred to the flip-flop. The system also includes means for selecting a desired one of the unit memory cells and an input-output circuit adapted to supply a data to the selected unit cell and deliver the data read out of the selected unit cell. The system further includes a source voltage variation detector circuit adapted to deliver, when the source voltage for the memory array circuit is rendered ON, a control signal including a readout signal for reading the data in the MNOS transistors into the flip-flop or a source voltage variation detector circuit adapted to generate a control signal including a write signal for writing a data in the flip-flop circuit into the MNOS transistors when the source voltage is rendered OFF and a readout signal for reading the data in the MNOS transistors into the flip-flop circuit when the source voltage is rendered ON, and means for interrupting in synchronism with the control signal a data transfer path between the selected unit memory cell and the input-output circuit so as to prevent any influence from an external circuit when a data transfer is effected between the flip-flop circuit and the MNOS transistors.
REFERENCES:
patent: 3983544 (1977-03-01), Dennison et al.
Fears Terrell W.
Tokyo Shibaura Electric Co. Ltd.
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