Non-volatile RAM cell with single high voltage precharge

Details Non-volatile RAM cell with single high voltage precharge Non-volatile RAM cell with single high voltage precharge

1985-11-25

1987-08-11

Moffitt, James W.

Static information storage and retrieval

Addressing

365154, 365185, 365203, G11C 800

Patent

active

046866523

ABSTRACT:
A memory cell circuit for storing the state of a digital signal on a data bus in response to an address signal. The memory cell has a store cycle with a repeating series of recurring store cycle sequences, each store cycle sequence having a (HIV) high-voltage timing signal during a first interval, and first and second store timing signals. The memory cell circuit also has a recall cycle. Each recall cycle has a memory reset signal to pre-set the state of the memory cell circuit during a first interval, a recall output signal at a predetermined voltage level and a recall transfer signal. The memory cell comprises a volatile RAM cell having a flip-flop providing an output signal at an output terminal. The flip-flop also has a RESET TERMINAL responsive to a reset signal for forcing the flip-flop to assume a predetermined state in response to the memory reset signal and a SET TERMINAL responsive to a set signal for setting the state of the volatile RAM cell in a recall sequence. A non-volatile RAM element has a rectifier capacitor means responsive to the high voltage timing signal for precharging to a first state during the first timing interval of each store cycle. Transfer control circuit means is responsive to the first store timing signal to discharge the capacitor in response to the flip-flop output signal being in a first state. The capacitor remains precharged in response to the flip-flop output signal being in a second state. A charge storage memory stores a state corresponding to the charge state of the capacitor into a non-volatile charge storage element. The charge storage memory provides a set signal corresponding to the state of the capacitor. The transfer control circuit couples the set signal to set the state of the flip-flop to correspond to the charged state of the charge storage device.

REFERENCES:
patent: 4091460 (1978-05-01), Schuermeyer et al.
patent: 4271487 (1981-06-01), Craycraft et al.
patent: 4375086 (1983-02-01), Van Velthoven
patent: 4510584 (1985-04-01), Dias et al.
patent: 4545035 (1985-10-01), Guterman et al.

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