Non-volatile programmable read only memory device having a plura

Details Non-volatile programmable read only memory device having a plura Non-volatile programmable read only memory device having a plura

1991-07-25

1994-03-01

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

36518911, 36523006, G11C 1140

Patent

active

052914402

ABSTRACT:
An electrically erasable and programmable read only memory device includes a plurality of series combinations of memory cells arranged in rows and columns, bit lines, a plurality of word lines, and a source line. Each bit line of the plurality of bit lines is respectively coupled to a front memory cell of the series combinations in one of the columns. The source line is coupled to rearmost memory cells of the plurality of series combinations of each of the columns. Each of the word lines is respectively coupled to each row of the memory cells. Each of the memory cells is implemented by a parallel combination of a floating gate field effect transistor coupled to a first word line and a switching transistor coupled to a second word line. The device is capable of performing selective write operations and simultaneously erasing the series combination of memory cells. The floating gate field effect transistors are formed on a major surface of a semiconductor substrate. The switching transistors are provided over the floating gate field effect transistor. Thus, the plurality of series combinations occupy a small area of the semiconductor substrate even though each memory cell includes both the switching transistor and the floating gate field effect transistor.

REFERENCES:
patent: 4630089 (1986-12-01), Sasaki et al.
patent: 4633438 (1986-12-01), Kume et al.
patent: 4667217 (1987-05-01), Janning
patent: 5060034 (1991-10-01), Shimizu et al.
patent: 5191551 (1993-03-01), Inoue

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