Non-volatile piezoelectric memory transistor

Details Non-volatile piezoelectric memory transistor Non-volatile piezoelectric memory transistor

1984-10-09

1986-05-13

Carroll, James J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 235, 357 234, 357 2315, 357 26, 357 41, 357 59, 365185, H01L 2978, H01L 2984, H01L 2702, H01L 2904

Patent

active

045890099

ABSTRACT:
A piezoelectric double diffusion MOS structure in which three gates are inserted in the CVD oxide element. These gates are overlapped layers of CVD polysilicon on top of the ZnO and are capacitively coupled to the silicon substrate. The charge is placed on the middle floating gate and is retained because of the oxide layers which separate the gates. A program erase, gate is provided for discharging the floating gate and to set the modes.

REFERENCES:
patent: 3585415 (1971-06-01), Muller et al.
patent: 3878549 (1975-04-01), Yamazaki et al.
patent: 4161039 (1979-07-01), Rossler
K. W. Yeh et al., "Detection of Acoustic Waves with a PI-DMOS Transducer," apanese Journal of Applied Physics , vol.16 (1977), Supplement 26-1, pp. 517-521.

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