Non-volatile NAND type semiconductor memory device with...

Details Non-volatile NAND type semiconductor memory device with... Non-volatile NAND type semiconductor memory device with...

1999-12-21

2001-02-20

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185010, C257S316000

Reexamination Certificate

active

06191975

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device and more particularly to techniques for allowing for high integration and high performance of a non-volatile semiconductor memory device using electrically alterable memory cells each having a two-layered gate structure of a charge storage layer and a control gate layer.
Conventionally there is known a form of electrically erasable programmable read only memory (EEPROM) in which MOS transistor-structured memory cells each having a multilayered structure of a charge storage layer and a control gate layer are arranged in a matrix.
FIG. 11
is a fragmentary plan view of an EEPROM of a NAND cell array in which each NAND cell comprises a plurality of memory cells connected in series. A plurality of signal lines BLj (shown for j=1 to 3; hereinafter referred to as bit lines) and a common line (hereinafter referred to as a source line) are connected to memory cells M(i, j) (shown for i=1 to 16 and j=1 to 3) through bit line contacts and source line contacts, respectively. The source line is connected to a reference voltage (e.g., ground potential).
In each column, memory cells M(
1
, j) to M(
16
, j) are series-connected so that adjacent memory cells share a diffused layer serving as a source/drain, thus forming a NAND cell.
The memory cells each have a multilayered gate structure of a charge storage layer (hatched by broken lines in
FIG. 11
) and a control gate layer for controlling an amount of charge stored in the charge storage layer. The charge storage layer is isolated from adjacent ones between each bit line. The control gate layers of the memory cells in each row are contiguous to be formed into one of word lines WLi (i=1 to 16) that intersect the bit lines BLj (j=1 to 3). Each word line WLi is connected to one memory cell M(i, j) for each bit line BLj.
To selectively write into and read from the memory cells, each NAND cell further comprises two select gate cells S(k, j) (k=1, 2, j=1 to 3) connected to both ends of the series-connected memory cells M(i, j).
That is, the two select gate cells S(k, j) are placed adjacent to the bit line contact and the source line contact. The memory cells M(i, j) and the two select gate cells S(k, j) are formed in each device region that extends in the direction of length of the bit lines Bj so that adjacent ones share a source/drain diffused region. The device regions are isolated by device isolation regions.
The switching control of the select gate cells S(k, j) is performed by two select gate lines SGk (k=1, 2). One of the select gate lines is provided on the bit line side and the other of the select gate lines is provided on the source line side. As an alternative, two or more select gate cells may be placed on each side.
FIG. 12
is a sectional view taken along line XII—XII of FIG.
11
.
The memory cell M(i,
1
) and the select gate cell Sk
1
are each formed from a silicon substrate (p-well region)
1
, n-type diffused layers la serving as source/drain regions, a first gate insulating layer
4
made of a thin silicon oxide film formed on the substrate, a charge storage layer
5
made of polysilicon, a second gate insulating film
6
formed on the charge storage layer
5
at a thickness larger than the first gate insulating layer, and a control gate layer
7
made of polysilicon.
The charge storage layer
5
in the memory cell M(i, j) is left floating and the tunnel injection of electrons from the n-type channel of the memory cell into the charge storage layer allows the memory cell to be written into. At this point, a write control voltage is applied to the control gate layer
7
. The operation of the EEPROM will be described in detail later.
The EEPROM of
FIG. 12
further comprises an interlayer insulating film
8
, a bit line (BL
1
)
9
, a bit line contact
10
, a source line
11
, and a source line contact
12
. A sectional view taken along line XIII—XIII of
FIG. 11
is shown in FIG.
13
.
In
FIG. 13
, like reference numerals are used to denote corresponding parts to those in FIG.
12
. WL
1
is a word line
13
that is made of a continuous control gate layer
7
. The memory cells M(
1
, j) (j=1 to 3) are isolated by isoplanar-type device isolation regions
3
a.
In the cross sectional structure of
FIG. 12
, the select gate cell Sk
1
, like the memory cell M(i, j), has a multilayered gate structure of charge storage layer
5
and control gate layer
7
. It has been thought heretofore that there is no need of providing a charge storage layer
5
in particular in the select gate cell Sk
1
because the select gate cell is no more than a switching transistor used to selectively write data into or read data from the memory cells.
If the select gate cell is formed to have the same gate structure as the memory cell as shown in
FIG. 12
, then the mask alignment process will become simple in comparison with the case where each of them has a separate structure, which is favorable for high-density integration. For this reason, in many cases the select gate cell is also formed with the charge storage layer as in the case of the memory cell and contact is then made to the charge storage layer.
As an example, a conventional method to make contact to the charge storage layer of the select gate cell on the bit line side is illustrated in FIG.
14
. The charge storage layer (FG) indicated by right-downward broken lines (and partially by right-downward continuous lines) and the control gate layer (CG) indicated by left-downward continuous lines indicate the planar shape of the charge storage layer
5
and the control gate
7
.
SG
1
indicates the select gate on the bit line side and WL
1
indicates a word line adjacent to SG
1
. Vertical dash-dotted lines indicate the boundaries of the device isolation region. Vertical dashed lines on the WL
1
indicate the edges of the respective FGs in the device isolation region. The FG portions formed below the CG are indicated by broken lines.
As shown in
FIG. 14
, in the select gate SG
1
a FG is made of a continuous layer over the whole area thereof. A portion of the CG is removed in the device isolation region and the FG in the contact area is broadened in the form of a pad to make contact to the FG. Thus, alignment margin for the contact portion is needed, which prevents high-density integration of EEPROM. On the other hand, as shown by the vertical broken lines on the word lines in
FIG. 11
, the memory cell charge storage layers
5
associated with adjacent bit lines are isolated from each other in the device isolation region. In the plan view of
FIG. 11
, vertical broken lines indicating the boundaries of the charge storage layers
5
are not shown in the select gate cells S(k, j) connected to the select gates SG
1
and SG
2
; for, in practice, the continuous charge storage layer is formed as shown in FIG.
14
.
In
FIG. 11
, the contact portion for the charge storage layer and the control gate layer shown in
FIG. 14
is omitted. In
FIG. 14
, the boundaries of the charge storage layers are shown by vertical broken lines on WL
1
because they are isolated from each other in the device isolation region.
FIG. 15
is a plan view of a mask pattern used in a lithography process for separating the charge storage layer between each bit line after the deposition of polysilicon as the charge storage layers of the respective memory cells M(i, j). In
FIG. 15
, M(
1
, j) (j=1 to 3) and S
1
j (j=1 to 3) indicate areas where memory cells and select gate cells are to be formed, respectively. WL
1
and SG
1
are a word line and a select gate, respectively.
It is required to remove a portion of the charge storage layer of the memory cells M(
1
, j) connected to the word line WL
1
between each bit line, but the charge storage layer of the select gate cells S
1
j connected to the select gate SG
1
is left continuous as shown in FIG.
15
.
Thus, the mask pattern shown in
FIG. 15
will have to be provided, as shown by arrows in
FIG. 15

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