Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2002-05-24
2004-09-21
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000
Reexamination Certificate
active
06794914
ABSTRACT:
BACKGROUND
1. Field
The invention relates to the field of Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. More particularly, the invention relates to Multi-Threshold CMOS circuits and devices capable of operating in active and sleep modes.
2. Description
Modern Integrated Circuits (IC's) are designed to provide an enormous amount of functionality in a small area. Very large scale IC's are able to provide nearly all the functions required in many electronic devices. The ability to incorporate vast processing power and multiple functions has made IC's nearly indispensable in portable electronic devices. Portable electronic devices, such as notebook computers, personal digital assistants, and cellular phones require IC's that have the ability to perform highly complex tasks. Portable electronic device designers, in turn, are committed to increasing the functionality of the device, while reducing its physical size.
One method of increasing the functionality of a portable electronic device is to increase the number of functions performed by the IC's. However, in order to keep the size of the IC from becoming prohibitively large, IC designers have been decreasing the physical size of the transistors used in the circuit design. The dimensions of the transistors used in a typical IC are limited by the techniques used to create them. Presently, IC transistors have dimensions on the order of sub-microns. For example, in sub-micron IC technology, the length (L) of a Metal Oxide Semiconductor (MOS) transistor may be less than 1 &mgr;m.
The physical size of portable electronic devices cannot be decreased merely by incorporating more functionality into the IC's. Increases in the complexity and functionality of the IC scales the power consumption of the IC proportionally. Because most portable electronic devices are battery powered, power consumption plays an important part in determining the useful operational time of a portable device. Increasing the capacity of the battery may increase the operational time of a portable device, however, this option is in conflict with the desire to decrease the physical size and weight of portable devices. Thus, there is a corresponding need to reduce the power consumed in the portable electronic device. Decreasing the power consumption allows the designer to incorporate a battery having smaller capacity, and typically smaller physical size.
Electronic devices may further conserve power by implementing sleep modes in some or all of the circuits within the device. For example, a paging device may sleep during defined time periods and only monitor paging messages during an assigned time slot. Similarly, a mobile telephone may control portions of the phone to enter sleep mode while the phone is powered on but is not in the process of communicating. The electronic devices would typically alternate between sleep and active modes per the needs of the device. It may be appreciated that nearly all portable electronic devices incorporate a sleep mode. For example, paging devices, telephones, notebook computers, wireless communication devices, personal digital assistants, and other electronic devices may include sleep modes where at least a portion of the circuits are put into a reduced power consumption mode.
The IC designer is thus tasked with increasing the complexity of the IC while simultaneously decreasing the power consumption. One manner of decreasing the power consumed by the IC is by judicious selection of the type of technology used in implementing the IC. An IC may be implemented using a variety of technologies. For example, circuits may be implemented using bipolar transistors, Metal Oxide Semiconductor (MOS) transistors, NMOS transistors, and Complementary MOS (CMOS) transistors. CMOS transistor implementations are particularly favored in digital designs because a CMOS gate, theoretically, consumes no power in a static state.
A diagram of a typical CMOS inverter
100
is shown in FIG.
1
. CMOS technology uses both n-channel and p-channel circuits in the same chip. The source of an n-channel MOS transistor
120
is connected to a voltage return, which may also be referred to as a voltage common, voltage reference, voltage return, or a ground. It may be appreciated that the voltage return may also be one of the power supply lines. The voltage return provides the reference for a corresponding power supply line, Vdd. The voltage return may be isolated from other circuits or may be common to the voltage return used in other circuits. The gate of the n-channel MOS transistor
120
is electrically connected to the gate of a p-channel MOS transistor
110
. The common gate connection also serves as the input to the CMOS inverter
100
. The source of the p-channel MOS transistor
110
is electrically connected to the power supply line, Vdd. The drain of the p-channel circuit
110
is electrically connected to the drain of the n-channel circuit
120
. The common drain connection is the output of the inverter
100
.
The operation of the inverter
100
is relatively simple. When the input signal, Vin, is low, the n-channel transistor
120
does not conduct, or is cut-off. However, the p-channel circuit
110
is switched on such that the power supply voltage, Vdd, appears at the output, Vout, of the inverter
100
. Alternatively, when the input signal, Vin, is high, the p-channel transistor
110
does not conduct and the n-channel circuit
120
is switched on, such that the output of the inverter
100
is pulled to voltage return. For each of the two states of the inverter
100
, one transistor of the complementary transistor pair is non-conducting. The non-conducting transistor provides a high impedance path from the power supply line to voltage return, thus limiting the power dissipation of the inverter
100
when the output is static. The leakage current of the cut-off transistor largely determines the level of power dissipation in the static state.
Power is consumed by the CMOS inverter
100
, and CMOS circuits in general, when the circuit switches between logic states. The power dissipation of the inverter
100
is proportional to the amount of energy provided to a load capacitance at each level transition. Thus, the power dissipation of the CMOS inverter
100
is proportional to C
L
*Vdd
2
*f. The value C
L
represents the load capacitance, Vdd represents the power supply voltage, and f represents the rate of change of the data.
It may be appreciated that for clocked sequential circuits, power dissipation is proportional to the clock frequency. Although the clock frequency depends largely on data throughput requirements, the clock signal to a number of circuits may be halted during periods in which the circuit is not required to be active. These periods of inactivity may include sleep modes where a portion of an IC is powered down to further conserve power. Largely, the rate of the clock signal cannot be slowed to save power without adversely affecting processing capability.
Perhaps the greatest improvements in CMOS power consumption can be made by reducing the power supply voltage. As indicated by the formula listed above, power dissipation is proportional to the square of the power supply voltage, Vdd. Thus, reductions in the power supply voltage provide greater power savings over comparable reductions in the operating frequency or the load capacitance.
However, reducing the power supply voltage adversely affects the propagation delay of CMOS circuits. As the power supply voltage is reduced to the threshold voltage of the MOS transistor, Vth, the propagation delay increases. The increase in propagation delay greatly degrades the ability of the CMOS gate to function in a high speed circuit.
One manner of decreasing the propagation delay, and thereby increasing the ability of the gate to function in a high speed circuit, is to reduce the threshold voltage, Vth, of the MOS transistors. However, a decrease in the threshold voltage results in an increase in the sub-threshold leakage current of the MOS transisto
Sani Mehdi Hamidi
Uvieghara Gregory A.
Brown Charles D.
Lam Tuan T.
Loomis Timothy F.
Qualcomm Incorporated
Wadsworth Philip R.
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