Non-volatile metal nitride oxide semiconductor device

Details Non-volatile metal nitride oxide semiconductor device Non-volatile metal nitride oxide semiconductor device

1975-12-31

1977-04-12

James, Andrew J.

357 23, 357 52, 357 37, 357 91, H01L 2934, H01L 2978, H01L 2900, G11B 1300

Patent

active

040178889

ABSTRACT:
A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

REFERENCES:
patent: 3867204 (1975-02-01), Rutledge
patent: 3875567 (1975-04-01), Yamazaki et al.
patent: 3891468 (1975-06-01), Ito et al.
patent: 3943542 (1976-03-01), Ho et al.
IBM Technical Disclosure Bulletin; Built-in Channel FET, by Chang, vol. 14, No. 4 Sept. 1971 pp. 1279 and 1280.
IBM Technical Disclosure Bulletin; Short Channel Field-Effect Transistor; by Abbas et al.; vol. 17, No. 11 Apr. 1975 p. 3263.

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