Non-volatile memory with two adjacent memory cells sharing...

Details Non-volatile memory with two adjacent memory cells sharing... Non-volatile memory with two adjacent memory cells sharing...

2006-11-21

2006-11-21

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290, C365S230030

Reexamination Certificate

active

07139193

ABSTRACT:
A nonvolatile semiconductor memory device having a small layout size includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes a plurality of element isolation regions. Each of the memory cells includes a source region, a drain region, a channel region located between the source region and the drain region, a select gate and a word gate disposed to face the channel region, and a nonvolatile memory element formed between the word gate and the channel region. A wordline connection section which connects at least one of a plurality of word gate interconnects in an upper layer with at least one of the word gates is disposed over at least one of the element isolation regions.

REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6069824 (2000-05-01), Kojima et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6587380 (2003-07-01), Kanai et al.
patent: 6587381 (2003-07-01), Kanai et al.
patent: 6646916 (2003-11-01), Kamei
patent: 6650591 (2003-11-01), Owa
patent: 6654282 (2003-11-01), Kanai
patent: 6697280 (2004-02-01), Natori
patent: 6704224 (2004-03-01), Natori
patent: 6707695 (2004-03-01), Owa
patent: 6707716 (2004-03-01), Natori
patent: 6707720 (2004-03-01), Kamei et al.
patent: 6707742 (2004-03-01), Kamei
patent: 6710399 (2004-03-01), Kamei
patent: 6717854 (2004-04-01), Natori
patent: 6738291 (2004-05-01), Kamei
patent: 6744106 (2004-06-01), Kanai
patent: 6757197 (2004-06-01), Kamei
patent: 6759290 (2004-07-01), Ogura et al.
patent: 6760253 (2004-07-01), Kamei
patent: 6762960 (2004-07-01), Natori
patent: 2002/0191453 (2002-12-01), Owa
patent: 2003/0022441 (2003-01-01), Ogura et al.
patent: 2003/0025149 (2003-02-01), Kanai
patent: 2003/0025150 (2003-02-01), Kanai et al.
patent: 2003/0027411 (2003-02-01), Kanai
patent: 2003/0072191 (2003-04-01), Kamei
patent: 2003/0072194 (2003-04-01), Kamei
patent: 2003/0085443 (2003-05-01), Natori
patent: 2003/0151070 (2003-08-01), Natori
patent: 2003/0164517 (2003-09-01), Kamei
patent: 2003/0174558 (2003-09-01), Kamei
patent: 2003/0179609 (2003-09-01), Natori
patent: 2003/0198102 (2003-10-01), Kamei et al.
patent: 2003/0198103 (2003-10-01), Kamei
patent: 2004/0013018 (2004-01-01), Kanai
patent: 2004/0013027 (2004-01-01), Kanai
patent: 2004/0061139 (2004-04-01), Natori
patent: 2004/0151045 (2004-08-01), Kanai
patent: 2004/0228181 (2004-11-01), Maemura
patent: 2004/0228185 (2004-11-01), Owa
patent: 2004/0229407 (2004-11-01), Owa
patent: 2004/0232474 (2004-11-01), Maemura
patent: 2005/0001261 (2005-01-01), Natori
patent: 05-266678 (1993-10-01), None
patent: 06-151782 (1994-05-01), None
patent: A 6-181319 (1994-06-01), None
patent: A 7-161851 (1995-06-01), None
patent: A 11-74389 (1999-03-01), None
patent: B1 2978477 (1999-09-01), None
patent: A 2001-156188 (2001-06-01), None
patent: 2002-353346 (2002-12-01), None
patent: 2002-357863 (2002-12-01), None
patent: 2003-037191 (2003-02-01), None
Hayashi et al. “Twin MONOS Cell with Dual Control Gates”, 2000 Symposium on VLSI Technology Digest of Technical Papers.
Chang et al. “A New SONOS Memory using Source-Side Injection for Programming”, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Chen et al. A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN), 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.

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