Non-volatile memory with reduced charge fluence

Details Non-volatile memory with reduced charge fluence Non-volatile memory with reduced charge fluence

2008-01-16

2010-11-30

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185240, C365S185290, C365S185180

Reexamination Certificate

active

07843730

ABSTRACT:
A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the integrated circuit using a second fluence, wherein the second NVM bit has a second transconductance, and wherein the first transconductance is greater than the second transconductance and the second fluence is greater than the first fluence.

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PCT/US2009/0300080 International Search Report and Written Opinion.

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