Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-27
2001-08-28
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S189070, C365S189090, C365S207000
Reexamination Certificate
active
06282120
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to floating gate semiconductor memories such as electrically erasable programmable read-only memories (EEPROM) and flash EEPROM, and specifically to circuits and techniques for reading or sensing their memory states.
BACKGROUND OF INVENTION
EEPROM and electrically programmable read-only memory (EPROM) are typically used in digital circuits for non-volatile storage of data or program. They can be erased and have new data written or “programmed” into their memory cells.
An EPROM utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over but insulated from a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate, but also insulated therefrom. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage (threshold) that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate.
The floating gate can hold a range of charge and therefore an EPROM memory cell can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window, delimited by the minimum and maximum threshold levels of the device, depends on the device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level within the window may, in principle, be used to designate a definite memory state of the cell.
In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding threshold voltage may be detected, or equivalently, a corresponding conduction current with respect to a reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
For EPROM memory, the transistor serving as a memory cell is typically programmed to one of two states by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. The memory states are erasable by removing the charge on the floating gate by ultraviolet radiation.
An electrically erasable and programmable read-only memory (EEPROM) has a similar structure but additionally provides a mechanism for removing charge from its floating gate upon application of proper voltages.
An array of such EEPROM cells is referred to as a “Flash” EEPROM array when an entire array of cells, or significant group of cells of the array, is erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed.
FIG. 1
illustrates schematically a typical array of non-volatile memory cells
10
, such as EPROM, EEPROM or flash EEPROM, accessible by a series of bit lines
20
,
22
,
24
, . . . , and word lines
30
,
32
, . . . Each memory cell
40
has a source
43
, a drain
44
, a control gate
46
and a floating gate
48
.
A specific cell in a two-dimensional array of EPROM or EEPROM cells is addressed for reading typically by application of a source-drain voltage to a pair of source and drain lines in a column containing the cell being addressed, and application of a control gate voltage to a word line connected to the control gates in a row containing the cell being addressed.
FIG. 2
shows schematically an addressable array of non-volatile memory cells
10
with row and column decoding circuits
50
,
52
and a read circuit
60
.
Referring also to
FIG. 1
, when the cell
40
is addressed for programming or reading, appropriate programming or reading voltages (V
CG
, V
S
, V
D
) must be supplied respectively to the cell's control gate
46
, source
43
and drain
44
. An address is applied to the row decoder
50
for connecting V
CG
to the word line
30
which in turn is connected to the control gate of the cell
40
. The same address is also applied to the column decoder
52
for connecting V
S
to the source line
20
and V
D
to the drain line
22
, which are respectively connected to the source and drain of the cell
40
.
The memory state of the addressed memory cell
40
is read with the read circuit
60
placing the appropriate operating voltages across the cell's source and drain, and then detecting the level of conduction current flowing between the source and drain.
In the usual two-state EEPROM cell, at least one current breakpoint level is established so as to partition the conduction window into two regions. When a cell is read, its source/drain current is resolved into a memory state by comparing with the breakpoint level (or reference current I
ref
). If the current read is higher than that of the breakpoint level or I
ref
, the cell is determined to be in one logical state (e.g., a “zero” state), while if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a “one” state). Thus, such a two-state cell stores one bit of digital information. A reference current source which may be externally programmable is often provided as part of a memory system to generate the breakpoint level current.
When a cell is programmed to a given state, it is subject to successive programming voltage pulses, each time adding incremental charge to the floating gate. In between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state has been verified to be in a desired region of the partitioned conduction window.
For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. The information that a given EEPROM array can store is thus increased with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338.
FIG. 3A
illustrates a chunk of memory cells
1
to k being read by a bank of sense amplifiers SA
1
, . . . , SAk, according to the prior art. Each sense amplifier senses the source-drain current of the cell it is connected to. To increase read performance, a plurality of cells is typically read in parallel chunk-by-chunk. Thus, cell
1
,
2
, . . . , k is respectively read by sense amplifier
1
,
2
, . . . , k, and the outputs &PHgr;
1
, &PHgr;
2
, . . . , &PHgr;
k
are latched in a chunk shift register. When all bits of the chunk are stored in the chunk shift register, the chunk can be shifted out serially. In the example, the conduction window of each cell is partitioned by three breakpoints. Each sense amplifier senses the source-drain current of a cell in the chunk and resolves the current into a memory state by comparing it relative to three reference currents, I
ref1
, I
ref2
and I
ref3
. Therefore, the three breakpoints can in principle partition the conduction window into four regions representing four possible memory states of the cell.
However, in practice, owing to the noises found in both the sensed current of a cell and the reference currents it is compared to, if the two currents are close together within their error margins, the memory state of the cell cannot be determined definitely. To offset this, a cell is usually programmed well into a partitioned region. In this way, even if the verification or read has an error due to noise, a margin of safety has been programmed to enable the programmed state of the cell to be read correctly. This is accomplished by setting up a margin or a guard band around each breakpoint or reference cur
Cernea Raul-Adrian
Guterman Daniel
Lee Douglas
Tang Rushyah
Wang Chi-Ming
Lam David
Nelms David
SanDisk Corporation
Skjerven Morrill & MacPherson LLP
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