Static information storage and retrieval – Floating gate – Particular biasing
Patent
1988-05-16
1989-12-12
Moffitt, James W.
Static information storage and retrieval
Floating gate
Particular biasing
357 2311, G11C 1140, H01L 2978
Patent
active
048872385
DESCRIPTION:
BRIEF SUMMARY
The present invention concerns memories and, more particularly, electrically programmable non-volatile memories or electrically programmable read-only memories more commonly known as EPROMs. It relates more precisely to the manufacture of memories with floating grid. To obtain large storage capacity memories, for example memories that can store up to four megabits, the dimensions of each cell constituting the memory should be reduced as far as possible.
However, there are obvious limitations imposed by physical factors and, especially, by the delicacy of the patterns which is made possible by photolithography. There are also limits imposed by unwanted electrical parameters which arise from the manufacturing process and disturb the operation of the memory.
Except a few exceptions, which have not yet achieved success on an industrial scale, all the approaches by which it has been sought to obtain large capacity memories correspond to a technology having the following features: made with a first level of polycrystalline silicon and a control grid made with a second level of polycrystalline silicon, Vss, polycrystalline silicon level, (aluminum) that intersects the word lines and makes contact with the drain of the transistors from place to place, for two adjacent drains of two transistors of the same column, this contact providing the connection to the bit line; similarly only one contact is provided between the sources of two adjacent transistors and the Vss bus, oxide (thick as compared with the oxide of the transistor grids), and the bit lines and word lines pass above this thick layer of oxide, follows: the sources of all the transistors of the memory are at a low potential Vss (for example zero volt); the word line connected to the control grid of the cell to be programmed is raised to a programming voltage Vpp (for example 15 volts) while all the other word lines are at the low potential Vss; the bit line corresponding to the cell to be programmed is raised to a high potential Vcc (for example 10 volts) while the bit lines of the cells which should not be programmed are held at the low potential Vss. imperative that the drain of a transistor should be electrically insulated, by a thick layer of oxide, from the drain of the adjacent transistors of the same word line, failing which it will not be possible to program a particular memory cell without, at the same time, programming or deprogramming the other memory cells.
However, the thick layer of oxide which insulates two adjacent cells takes up a great deal of space, especially when it is made by the so-called localized oxidation technique.
Attempts have been made to replace localized oxidation by insulation with oxide-filled grooves to reduce the overall space factor of the cell, but this technology has not yet been implemented for industrial-scale manufacture.
To reduce the overall space occupied by the cells and thus increase the storage capacity of the memory, the present invention proposes a new memory architecture with which there is no need for insulation by a thick layer of oxide between adjacent transistors and yet allows to retain standard type manufacturing methods if so desired.
The invention also proposes a manufacturing method which is particularly suited to this architecture. According to the invention, the memory consists of an array of word lines, connecting cells in rows, and bit lines, connecting cells in columns, the word lines being conductors used to designate a specific row of cells and the bit lines being conductors used to transmit a piece of informamtion on the logic state of the cells connected to them, each cell, located at the intersection of a specific row and a specific column, comprising a transistor having a control electrode connected to a word line and two main electrodes (drain and source), one connected to a first bit line and the other connected to another bit line adjacent to the first bit line, this other bit line being itself connected to a main electrode of a transistor of a column adjacent to the specific column
REFERENCES:
patent: 4151021 (1979-04-01), McElroy
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4361847 (1982-11-01), Harari
patent: 4384349 (1983-05-01), 365
patent: 4727515 (1988-02-01), Hsu
Moffitt James W.
SGS Thomson-Microelectronics SA
LandOfFree
Non-volatile memory with floating grid and without thick oxide does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory with floating grid and without thick oxide, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory with floating grid and without thick oxide will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2126541