Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-06-21
2004-05-25
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S063000, C365S185050, C365S185160
Reexamination Certificate
active
06741498
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory, and more particularly, to a non-volatile memory that combines a main memory array region and a redundant memory array region.
2. Description of the Prior Art
Non-volatile memory presently includes a redundant memory array region adjacent to a conventional main memory array region. The redundant memory array region has the same structure as the main memory array region and is used to replace memory cells that have failed in the main memory array region. This design feature of non-volatile memory enhances defect tolerance during the manufacturing process and results in increased yield and memory size.
Please refer to FIG.
1
.
FIG. 1
is a block diagram of a conventional non-volatile memory
10
. The non-volatile memory
10
is positioned on a substrate (not shown) of a semiconductor wafer. The non-volatile memory
10
comprises a peripheral circuit region
20
and a memory array region
50
. The memory array region
50
comprises a main memory array region
60
and a redundant memory array region
80
. The peripheral circuit region
20
comprises an address buffer
22
, an addressable memory unit
24
used for storing address data of failed memory cells in the main memory array region
60
, a main memory ground line decoder
26
electrically connected to a plurality of ground lines GL in the main memory array region
60
, a main memory bit line decoder
27
, a redundant memory ground line decoder
28
electrically connected to a plurality of ground lines RGL in the redundant memory array region
80
, and a redundant memory bit line decoder
29
. Each bit line BL, RBL is electrically connected to a pass transistor. The main memory bit line decoder
27
is electrically connected to a gate of the pass transistor, and the redundant memory bit line decoder
29
is also electrically connected to a gate of the pass transistor to electrically connect each bit line BL, RBL to a data line.
Please refer to FIG.
2
A and FIG.
2
B.
FIG. 2A
is a structural schematic diagram of a memory array region
50
in a conventional non-volatile memory
10
, and
FIG. 2B
is a circuit diagram of a memory array region
50
in a conventional non-volatile memory
10
. The non-volatile memory
10
is positioned on a substrate
42
of a semiconductor wafer
40
. The memory array region
50
comprises a main memory array region
60
, a redundant memory array region
80
, a field oxide
70
positioned between the main memory array region
60
and the redundant memory array region
80
and used to divide the main memory array region
60
from the redundant memory array region
80
, and two dummy memories
72
positioned on each side of the field oxide
70
that are used to prevent the main memory array region
60
and the redundant memory array region
80
from being affected by the field oxide
70
during the fabrication process.
The main memory array region
60
comprises M bit lines BL
1
to BL
M
, M+1 ground lines GL
1
to GL
M+1
, and a plurality of memory cells. Each memory cell comprises a source
56
and a drain
54
positioned in the substrate
42
of the semiconductor wafer
40
, and a gate
58
positioned on the substrate
42
. Each ground line GL is electrically connected to the sources
56
of a predetermined number of memory cells, and each bit line BL is electrically connected to the drains
546
of a predetermined number of memory cells in the main memory array region
60
. Among M+1 ground lines, GL
2
to GL
M
are used for operating the memory cells on either side of the ground line. That is, ground lines GL
2
to GL
M
are shared by the memory cells positioned on either side of the respective ground line, and ground lines GL
1
and GL
M+1
are used for operating memory cells on only one side of the ground line. Additionally, BL
1
to BL
M
are used for operating the memory cells on either side of the bit line. That is, bit lines BL
1
to BL
M
are shared by the memory cells positioned on either side of the respective bit line.
The redundant memory array region
80
comprises N bit lines RBL
1
to RBL
N
, N+1 ground lines RGL
1
to RGL
N+1
, and a plurality of memory cells. Each memory cell comprises a source
56
and a drain
54
positioned in the substrate
42
of the semiconductor wafer
40
, and a gate
58
positioned on the substrate
42
. Each ground line RGL is electrically connected to the sources
56
of a predetermined number of memory cells in the redundant memory array region
80
, and each bit line RBL is electrically connected to the drains
54
of a predetermined number of memory cells in the redundant memory array region
80
. Among the N+1 ground lines, RGL
2
to RGL
N
are used for operating the memory cells on either side of the ground line. That is, ground lines RGL
2
to RGL
N
are shared by the memory cells positioned either side of the respective ground line, and ground lines RGL
1
and RGL
N+1
are used for operating the memory cells on only one side of the ground line. Additionally, RBL
1
to RBL
N
are used for operating the memory cells on either side of the bit line. That is, bit lines RBL
1
to RBL
N
are shared by the memory cells positioned on either side of the respective bit line.
Please refer to FIG.
2
B. When a memory cell M
2
in the non-volatile memory
10
is accessed, it is necessary to address a ground line GL
2
, a bit line BL
1
, and a word line WL
1
to control a source
56
, a drain
54
, and a gate
58
, respectively. The address buffer
22
passes an address signal to the addressable memory unit
24
, the main memory ground line decoder
26
, the main memory bit line decoder
27
, the redundant memory ground line decoder
28
, and the redundant memory bit line decoder
29
. The main memory ground line decoder
26
decodes the address signal to address the ground line GL
2
. The main memory bit line decoder
27
decodes the address signal to turn on each pass gate to address the bit line BL
1
. Addressing the word line WL
1
is performed in the same manner.
When the address signal corresponds with an address stored in the addressable memory unit
24
, the addressable memory unit
24
generates a corresponding signal to turn on the redundant memory ground line decoder
28
and the redundant memory bit line decoder
29
. The redundant memory ground line decoder
28
decodes the address signal passed from the address buffer
22
to address a redundant ground line. The redundant memory bit line decoder
29
decodes the address signal passed from the address buffer
22
to turn on each pass gate to address a redundant bit line.
In the conventional memory array region
50
of a non-volatile memory
10
, the field oxide
70
positioned between the main memory array region
60
and the redundant memory array region
80
and the two dummy memories
72
positioned on each side of the field oxide
70
are utilized to divide the main memory array region
60
from the redundant memory array region
80
. However, the field oxide
70
and the dummy memories
72
, which are incapable of storing data, increase the layout area of the memory array region
50
. Therefore, as the design dimensions of semiconductor products continue to shrink, it becomes increasingly important to reduce the area taken up by the field oxide
70
and the dummy memories
72
in order to increase the usable area of the memory array region.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a non-volatile memory with a combined main memory array region and redundant memory array region to solve the above-mentioned problem of the prior art.
The claimed invention provides a non-volatile memory without the field oxide and the dummy memory that are used to divide the main memory array region from the redundant memory array region. Moreover, the non-volatile memory has the main memory array region directly connected to the redundant memory array region. Furthermore, the non-volatile memory has a virtual gro
Ho Hoai
Macronix International Co. Ltd.
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