Non-volatile memory with background operation function

Details Non-volatile memory with background operation function Non-volatile memory with background operation function

2001-04-12

2003-02-04

Tran, M. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S233100

Reexamination Certificate

active

06515900

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, and particularly to a multi-bank, non-volatile semiconductor memory device having a plurality of banks. More particularly, the present invention relates to a flash memory (background operation (BGO) flash memory) having background operation function that allows, while an internal operation such as erasing/programming operation is being performed with respect to one bank, data to be read out from another bank.
2. Description of the Background Art
FIG. 25
schematically shows an entire configuration of a conventional BGO flash memory. Referring to
FIG. 25
, the conventional BGO flash memory includes a plurality of banks B#
1
-B#
4
. These banks B#
1
-B#
4
, each addressable independently of others, have essentially an identical configuration. Thus, in
FIG. 25
, reference characters for internal components of only bank B#
1
are representatively denoted.
Banks B#
1
-B#
4
each include: a memory array MA having a plurality of non-volatile memory cells arranged in rows and columns; a pre-decoder PD that pre-decodes an internal address signal from an address buffer
901
; a row decoder RD that decodes an internal row address (pre-decoded) signal from pre-decoder PD and selects an addressed row in memory array MA; a column decoder CD that decodes an internal column address signal (pre-decoded signal) from pre-decoder PD and generates a column select signal for selecting an addressed column in memory array MA; a Y gate YG for selecting a column in memory array MA according to the column select signal from column decoder CD; and a sense amplifier SA that senses and amplifies data on the column selected by Y gate YG.
Each of these banks B#
1
-B#
4
is further provided with a write circuit for transmitting a voltage corresponding to write data to a selected memory cell (bit line) in a write mode. The write circuit, however, is not shown in
FIG. 25
for simplification of the drawing.
The non-volatile semiconductor memory device further includes: a bank pointer
903
that decodes a bank address signal included in the internal address signal from address buffer
901
and generates a bank designating signal for selectively activating banks B#
1
-B#
4
; an internal control circuit
900
that takes in an externally supplied command CMD according to a control signal CTL and generates various internal control signals for performing an operating mode designated by the command CMD; a data buffer
913
that takes in externally supplied data according to control signal CTL and generates internal write data, and externally outputs the data in a read mode; a write data buffer
904
provided corresponding to banks B#
1
and B#
3
and latches the data supplied from data buffer
913
in a write mode; an erase/program verify circuit
905
provided corresponding to banks B#
1
and B#
3
and detects, in the erasing/programming operation, whether the erasing and programming operations are performed accurately; a write data buffer
906
provided corresponding to banks B#
2
and B#
4
and latches the internal write data from data buffer
913
; and an erase/program verify circuit
907
for detecting, in the erasing/programming operation of bank B#
2
or B#
4
, whether the erasing or the programming is performed accurately in the selected bank.
The write data in write data buffer
904
is supplied to the write circuits (not shown) of banks B#
1
and B#
3
, and an internal voltage corresponding to the write data is transmitted to an internal data line (bit line). Likewise, write data buffer
906
supplies the write data to the write circuits (not shown) of banks B#
2
and B#
4
, and a voltage corresponding to the write data is transmitted to a selected column of bank B#
2
or B#
4
.
In erasing/programming operation, the erasing and programming operations differ for different types of flash memories. In a NOR type flash memory, the erasing operation is an operation of lowering a threshold voltage of a transistor in a memory cell, which is done by drawing electrons out of a floating gate of the memory cell transistor. In a DINOR type flash memory, the erasing operation is an operation of raising the threshold voltage of the memory cell transistor by injecting electrons into the floating gate of the memory cell transistor. Likewise, in the programming operation, the threshold voltage of the memory cell transistor is raised in the NOR type flash memory, whereas the threshold voltage is lowered in the DINOR type flash memory.
In the erasing/programming operation, internal control circuit
900
performs, according to a verify result designating signal from erase/program verify circuit
905
or
907
, the erasing/programming operation repeatedly until the erasure or program is carried out accurately. In addition, internal control circuit
900
causes address buffer
901
to take in an externally supplied address signal AD according to command CMD and to generate, in the internal operation, an internal control address signal according to the address taken in.
Address buffer
901
generates both an internal address signal corresponding to the externally supplied address signal AD and the internal control address signal generated under the control of internal control circuit
900
. Bank pointer
903
can generate, according to the internal address signal and the internal control address signal from address buffer
901
, both an internal operating bank designating signal and a bank designating signal corresponding to the external address signal. By generating both the internal address signal corresponding to the external address signal AD and the internal control address signal generated under the control of internal control circuit
900
, it becomes possible, while the internal operation such as erasing/programming operation is being performed in one bank, to access another bank for reading out memory cell data.
The non-volatile semiconductor memory device further includes: a register circuit
908
that stores a device production code (ID code) specific to the device; a register circuit
909
that stores common flash interface (CFI) codes (normally 32 kinds of data) such as an erase cycle time and storage capacity; a register circuit
910
that stores status data indicating operating states of the banks; a register circuit
911
that stores lock bits indicating presence/absence of lock in banks B#
1
-B#
4
on a block basis; and an output switching circuit
912
that selects, according to a read mode switching signal RSW from internal control circuit
900
, one of data Di read out from these register circuits
908
-
911
and banks B#
1
-B#
4
, for application to data buffer
913
.
In this non-volatile semiconductor memory device, during the time where the erasing/programming operation is being performed in one bank, it is possible to access another bank or status register circuit
910
to read out necessary data. Such function (capability) that enables, while an internal operation is being performed in one bank, data to be read out from a circuit (the status register circuit or a bank) other than the bank currently subject to the internal operation, is called background operation (BGO) function (capability). Generally in a non-volatile semiconductor memory device, while data reading is done at a speed as high as 50 ns (nano seconds) to 100 ns, the erasing/programming operation requires a relatively long time on the order of 2 &mgr;s to 5 s. By enabling the access to one bank or the status register circuit during the erasing/programming operation of another bank, wait time of the system decreases, thereby improving processing efficiency of the system.
To perform such internal operation and data reading on a bank basis, each bank is provided with a sense amplifier SA.
FIG. 26
schematically shows a configuration of address buffer
901
shown in FIG.
25
. Referring to
FIG. 26
, a

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