Non-volatile memory system of multi-level transistor cells and m

Details Non-volatile memory system of multi-level transistor cells and m Non-volatile memory system of multi-level transistor cells and m

1995-08-15

1997-01-21

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

365104, 365184, 36518503, 36518524, G11C 1134

Patent

active

055965261

ABSTRACT:
A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

REFERENCES:
patent: 4586163 (1986-04-01), Koike
patent: 5163021 (1992-11-01), Mehrotra et al.

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