Non-volatile memory system having internal data verification tes

Details Non-volatile memory system having internal data verification tes Non-volatile memory system having internal data verification tes

1996-01-22

1997-10-07

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

365201, 3651853, 365236, G11C 2900

Patent

active

056755406

ABSTRACT:
A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.

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patent: 5416740 (1995-05-01), Fujita et al.
patent: 5428575 (1995-06-01), Fudeyasu
patent: 5463585 (1995-10-01), Sanada

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