Non-volatile memory structure and erase method with floating...

Details Non-volatile memory structure and erase method with floating... Non-volatile memory structure and erase method with floating...

2005-02-14

2008-03-04

Gurley, Lynne (Department: 2811)

Static information storage and retrieval

Floating gate

Particular biasing

Reexamination Certificate

active

07339835

ABSTRACT:
Feedback between the floating gate voltage and a high erase voltage is utilized in the erase operation of a non-volatile memory (NVM) cell. Erasing stops when the floating gate voltage reaches the threshold voltage of the controlling transistor, making the variability of the NVM cell's threshold voltage the same as a regular device in the integrated circuit structure, thereby reducing the significant threshold voltage variability in erased NVM cells.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5235541 (1993-08-01), Edme et al.
patent: 5736764 (1998-04-01), Chang
patent: 6137723 (2000-10-01), Bergemont
patent: 6914826 (2005-07-01), Hung et al.

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