Non-volatile memory structure

Static information storage and retrieval – Powering – Data preservation

Patent

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Details

361154, 361185, G11C 1300

Patent

active

050974491

ABSTRACT:
A non-volatile memory circuit for use with an E.sup.2 PROM includes redundant, parallel connected, floating node MOSFET memory cells for storing complementary information. The non-volatile memory cells are connected in parallel to a volatile memory circuit via a voltage level shifter circuit for writing operations, and via twin mixed PMOS and NMOS transistors for reading operations. With the combined complementary non-volatile memory cells and the twin mixed pairs of transistors, the stored information is retained in the event that one of the memory cells fails.

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