Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-10-29
2001-04-17
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185180, C365S196000, C365S205000, C365S210130
Reexamination Certificate
active
06219279
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention is in the field of non-volatile memories of the type having floating gates in the memory cells, such as EPROM, EEPROM and flash EEPROM systems, and, more specifically, directed to controlling the level of bit line current during programming of such memories and to generating a reference level used during reading the programmed states of cells in such memories.
Two techniques are commonly used for programming a floating gate memory cell. One technique causes electrons traveling through the cell's channel, from its source to its drain, to be imparted with enough energy to be injected onto the floating gate through a gate dielectric positioned therebetween. This is often termed “hot electron injection” programming. Another technique is to place appropriate voltages on the cell's source, drain and control gate to cause electrons to tunnel through the gate dielectric. This is usually referred to as “Fowler-Nordheim tunneling.” Each technique has its own advantages and disadvantages.
Hot electron programming requires that relatively high currents be passed through the cell in order to impart enough energy to electrons for injection onto the floating gate. This high current can cause a parasitic n-p-n bipolar transistor associated with the cell transistor to turn-on (snap back) and draw an excessive level of current through the cell and its column bit line. Therefore, others have attempted to limit current through bit lines during programming. One technique includes placing a resistor in the path of each bit line to limit it's current. The size of the resistor is chosen to be large enough to limit the current that may flow through a bit line and an addressed cell connected thereto but must also be made small enough to allow efficient programming. This necessary trade-off limits the effectiveness of the series resistance to control the high bit line current that can result when the addressed cell transistor goes into a snap back mode. Others have used active circuits connected to the bit lines but their use has proven difficult to adequately control the bit line current.
The state of a floating gate memory cell is usually read by impressing given voltages across the cell and on its control gate, and then reading the resulting current that flows through the cell. The amount of current that flows through the cell is related to the amount of charge on its floating gate. This current, or a voltage proportional to the current, is measured and compared with at least one reference that provides a breakpoint between programmed states of the cell. The result of this comparison is to measure the state into which the cell has been programmed.
SUMMARY OF THE INVENTION
According to a principal aspect of the present invention, a limit is placed on the amount of current that can be drawn through a bit line during the programming of one of its cells by biasing a bit line driving transistor to mirror the maximum desired current from another transistor and reference current source into the program driving transistor. This thus limits the maximum current through the cell being addressed, and is useful, for example, during hot electron programming when a relatively large current passing through the cell can initiate snap back. This prevents damage to the cells that can result from excessive currents being passed through them during programming, and also extends their life in terms of a maximum number of programming cycles that they can endure.
According to another aspect of the present invention, the state of a cell is monitored during programming by comparing the voltage of its bit line with a reference voltage that is generated with a circuit containing a transistor that is a replica of the memory array driving transistors. As a result, the current-voltage characteristic of the reference transistor is the same as that of the bit line driving transistors for a given integrated circuit chip, even as those characteristics vary among different chips from different wafers, and/or from wafers made in different processing batches. Differences between the monitored bit line voltage and the locally generated reference voltage are thus proportional to the programmed state of the cells and not the result of variations among different circuit chips.
In a preferred form, both of these aspects are combined together into a single bit line program driving and simultaneous reading circuit, wherein an excessive bit line current and an erroneous read reference level are avoided. The life of the memory and reading accuracy are then both improved. Alternatively, either of these improvements over existing non-volatile programming and reading techniques may be employed without the other.
In a specific example, the driving transistors, and thus also the reference level transistors in the improved reference generation circuit, are p-mos devices. This allows much better control of the driving transistor biasing and current control characteristics during programming than results ifn-mos devices are used for the driving transistors, since the sources of the p-mos transistors are connected to the programming voltage supply that is substantially constant. The gate-to-source voltage of the p-mos transistor drivers, which controls the level of conduction through them, are then accurately controlled by applying bias voltages to their gates as part of the current mirroring circuit.
Additional features and advantages of the present invention, in its various aspects and forms, are given in the following description of its embodiments, which description should be taken in conjunction with the accompanying drawings
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Manolescu Mihai
Spadini Gianpaolo
Nguyen Viet Q.
Skjerven Morrill & MacPherson LLP
Zilog Inc.
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