Non-volatile memory including charge-trapping layer, and...

Details Non-volatile memory including charge-trapping layer, and... Non-volatile memory including charge-trapping layer, and...

2007-11-06

2007-11-06

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185290

Reexamination Certificate

active

11222708

ABSTRACT:
A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the trench. The gate includes a p-doped semiconductor material, so that the memory cell is particularly suitable to erase through hole injection from the gate.

REFERENCES:
patent: 6844584 (2005-01-01), Palm et al.
patent: 6867455 (2005-03-01), Itoh et al.
patent: 7170785 (2007-01-01), Yeh
patent: 2007/0031999 (2007-02-01), Ho et al.
“UMEM: A U-shape Non-Volatile-Memory Cell” By Josef Willer et al. / IEEE NVSM 2003 / pp. 42-43.
“NROM: A Novel Localized Trapping, 2-Bit nonvolatile Memory Cell” By Boaz Eitan et al. / IEEE Electron Device Letter, vol. 21, No. 11, Nov. 2000 / pp. 543-545.

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