Non-volatile memory having charge correction circuitry

Details Non-volatile memory having charge correction circuitry Non-volatile memory having charge correction circuitry

1987-12-03

1989-01-24

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365210, 357 235, G11C 700, G11C 1140, G11C 2900

Patent

active

048005282

ABSTRACT:
A semiconductor device having one or more first non-volatile memory transistors and a detector having a second non-volatile memory transistor with which a charge level written in the first transistor is safeguarded and corrected, if necessary, by a suitable, incorporated bias voltage between source zone and control electrode and/or a margin fixed by an incorporated difference in threshold voltage. A further non-volatile memory transistor may be present with which there is detected, during writing, erasing or rewritting, whether the desired charge level in the first transistor is reached and the charge transport is to be terminated.

REFERENCES:
patent: 4218764 (1980-08-01), Furuta et al.
patent: 4371956 (1983-02-01), Maeda et al.
patent: 4404475 (1983-09-01), Drori et al.
Gerber et al., "Low Voltage Single Supply CMOS Electrically Erasable Read Only Memory", IEEE Transactions on Electron Devices, vol. ED-27, No. 7, Jul. 1980, pp. 1211-1216.

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