Non-volatile memory having a cell applying to multi-bit data by

Details Non-volatile memory having a cell applying to multi-bit data by Non-volatile memory having a cell applying to multi-bit data by

1995-11-21

1997-07-01

Nelms, David C.

Static information storage and retrieval

Floating gate

Multiple values

36518501, 36518518, G11C 1134

Patent

active

056445288

ABSTRACT:
An object of the present invention is to contribute to increase of storage capacity of a memory. A nonvolatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture. The memory has a storage cell transistor which comprises a semiconductor substrate 1, source 2, drain 3 and control gate 5. The storage cell transistor, furthermore comprises a plurality of floating gates 4B.sub.1 -4B.sub.n which are arranged in order between a channel and the control gate. Two or more bits data can be saved per one storage cell. According to this architecture, an integration factor per one storage cell leaps upward since a necessary number of floating gates are stacked to overlie each other, the particular number corresponding to the number of bits to be stored therein.

REFERENCES:
patent: 5159570 (1992-10-01), Mitchell et al.
patent: 5422845 (1995-06-01), Ong
A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, Shibata et al, IEE Transactions on Electron Devices, vol. 39, No. 6, Jun. 1992, pp. 1444-1455.
New Ultra-High Density Textured Poly-Si Floating Gate EEPROM Cell, Guterman et al, Reprint pp. 146-184 from IEDM Tech. Dig., pp. 826-828, Dec. 1986.

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