Non-volatile memory for storing erase operation information

Details Non-volatile memory for storing erase operation information Non-volatile memory for storing erase operation information

2001-02-01

2002-04-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185110, C365S218000

Reexamination Certificate

active

06377491

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to nonvolatile memory such as flash memory, and more particularly to nonvolatile memory that can store information relating to the history of erase operations.
2. Description of the Related Art
A flash memory, which is a nonvolatile memory device, not only can hold stored information even when the power is off, but also is smaller and can read information more quickly than a hard disk, and is therefore widely used as semi-conductor memory in mobile telephones and digital cameras.
Conventional flash memory writes information by applying a program pulse to cell in an erased state. Memory blocks are rewritten by applying a program pulse to the desired cells after firstly erasing the entire memory block. Flash memory can also erase a specified memory block in response to an external erase command. Usually, an erased state is data 1 and a written state (programmed state) where a program pulse has been applied is data 0. Writing and programming are used with the same meaning.
The above block erase operation comprises a preprogram process in which cell data in the memory block is read and all cells in an erased state are programmed (made into data 0) and an erase process in which all cells are then erased (made into data 1) while an erase pulse is applied to all cells in the memory block. When these two processes end normally, the block erase operation ends normally. Then, after that, data can be written to the memory block. In this erase operation an internal control circuit comprising a microprocessor executes a series of sequence programs in response to an erase command.
However, an erase operation can be interrupted when, for example, the power is cut during the above series of erase operations. Erase operations can also be interrupted when a user decides that the erase operation has failed because for some reason it does not end within a certain time. When an erase operation is thus interrupted, the state of cells within the memory block is not clear and information cannot be read normally from these memory cells of unclear state even after a program operation is executed. Also, when information cannot be read normally it is difficult to diagnose the cause. In particular, when interruption during an erase operation causes the threshold voltage to be neither data 1 nor data 0, a special detection circuit is required to detect the stage at which the error occurred. It is not practical to build such detection circuit into the device.
Of course, if it is determined that an erase operation was interrupted, cells can be returned to their normal erased state by executing the erase operation again, i.e. preprogramming all memory cells within the memory block, and then erasing all memory cells simultaneously. However, it is difficult to detect if an erase operation has been interrupted or at what stage of an erase operation it has been interrupted and therefore, when reading fails it is not efficient practice to repeat a block erase operation under the assumption that an erase operation has been interrupted.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a nonvolatile memory that can easily determine whether or not an erase operation has been interrupted.
A further object of the present invention is to provide a nonvolatile memory that can easily detect the stage at which an erase operation was interrupted.
To achieve the above objects, one aspect of this invention is nonvolatile memory that has an ordinary memory cell region wherein ordinary data is stored and an erase information storage memory region wherein the information that shows the status of the erase operation is stored. The erase information storage memory region comprises nonvolatile memory that can store the information even when the power is cut.
Preferably, the erase information storage memory region can store erase information in the memory block units in which the erase operation is executed. Further preferably, the erase information storage memory region is able to store erase information for at least the three statuses that are involved in erase operations: erase operation start status, preprogramming end status, and erase operation complete status.
In another preferred embodiment, the erase information in the erase information storage memory region can be read out to an external device, or read out to an external device in response to a prescribed command. Alternatively, the erase information can be read internally in response to the switching on of power or another prescribed command and then output the information to an external device when the erase information indicates a memory block in which an erase operation has been interrupted.
Furthermore, in another preferred embodiment, the erase information is read internally in response to a switching on of power or another prescribed command and, when the erase information indicates a memory block in which an erase operation has been interrupted, an erase operation can be automatically executed for that memory block.
The above nonvolatile memory stores erase information such as whether or not erase operations have ended normally for each memory block or the stage to which an erase operation has progressed, thereby simplifying diagnosis when a failure occurs and enabling an efficient return to a normal state.


REFERENCES:
patent: 5978273 (1999-11-01), Shigemura
patent: 6118704 (2000-09-01), Hirata
patent: 357200994 (1982-12-01), None
patent: 8-101788 (1996-04-01), None

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