Non-volatile memory embedded in a conventional logic process...

Details Non-volatile memory embedded in a conventional logic process... Non-volatile memory embedded in a conventional logic process...

2008-01-28

2009-12-15

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185280, C365S149000

Reexamination Certificate

active

07633810

ABSTRACT:
A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

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