Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-01-29
2003-10-21
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185020
Reexamination Certificate
active
06636442
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to non-volatile memory cells with both a select transistor and a floating gate storage transistor used with high density programmable logic devices (PLDs). More particularly, the present invention relates to a method for reducing field oxide stress and program disturb conditions in the memory cell.
2. Background
FIG. 1
shows a conventional two transistor non-volatile memory cell used with a PLD. The memory cell includes a nonvolatile floating gate storage transistor
100
, along with a conventional select memory transistor
102
. The select transistor
102
is used to prevent programming of the floating gate storage transistor
100
when the two transistor cell is in an array of memory cells and other cells on the same bitline are being programmed.
FIG. 2
shows a cross-section of the layout for the conventional two transistor memory cell of FIG.
1
. As shown, the floating gate storage transistor
100
is an NMOS device including an n+ type source region
200
and an n+ type drain region
202
provided in a p type substrate. The floating gate is a polysilicon region
204
with a portion
206
which creates a tunneling region in the oxide material
207
between the polysilicon gate
204
and the p type substrate. The floating gate
204
is provided over the channel in the substrate between the source
200
and drain
202
. A control gate
210
is provided above the polysilicon gate
206
, and is formed from a conductive material to which gate control signals are applied.
The select transistor
102
has a source
202
formed in common with the drain of the storage transistor
100
. An n+ type drain region
212
of the select transistor
102
is formed in the p substrate with a conductive gate region
214
overlying the channel between the source
202
and drain
212
. An oxide material
215
is provided between the gate
214
and channel of transistor
102
.
The select transistor
102
is used to prevent a program disturb condition. The program disturb condition can be a drain disturb event which occurs in a floating gate transistor in an unselected memory cell connected to the same bit line as a selected memory cell transistor. The high bit line program voltage and low unselect gate voltage applied to a floating gate storage transistor to prevent programming when a select transistor is not used causes a high electric field to be applied between the gate and drain of the floating gate transistor. The high electric field may cause electrons to tunnel between the floating gate and drain resulting in a drain disturb programming condition where the unselected cell is unintentionally programmed. Similarly, since the source electrode of the selected and unselected memory cells may be connected together on a bit line, a source disturb event can likewise cause an unintentional programming of unselected memory cells. A select transistor effectively blocks the bitline drain voltage from the storage transistor to prevent drain disturb or source disturb conditions.
With a high bit line programming voltage (Vpp) now applied to the drain of a select transistor
102
, avalanche breakdown can occur in the select transistor causing damage. With the high programming voltage applied to the bit line, and zero volts applied to the gate of the select transistor
102
, avalanche breakdown can occur through the oxide region
215
between the drain
212
and gate
214
resulting in damage to the oxide region
215
.
Instead of zero volts, an intermediate voltage (Vunselect) can be applied to the gate of select transistors in memory cells which are not to be programmed. The value of Vunselect is bounded by a “voltage box” on the high side by a soft programming condition, where insufficient voltage should be passed through to the programming element to allow any programming due to a disturb condition. The value of Vunselect is bounded on the low side by the oxide breakdown concerns where the voltage from the drain of the select device to the gate of the select device exceeds the intrinsic breakdown voltage of the insulating oxide film.
SUMMARY
In accordance with the present invention, a voltage box on select transistors of conventional memory cells is avoided.
In accordance with the present invention, a memory cell is provided including three transistors, a floating gate nonvolatile storage transistor and two cascode connected select transistors. The two cascoded select transistors act together to block the bit line programming voltage when the memory cell is connected in an array, and the cell is not selected for programming. A value of an unselect voltage (Vunselect
1
) applied to the gate of the first cascode connected transistor connected directly to the bit line can be set to eliminate the select transistor oxide breakdown concern. A value of an unselect voltage (Vunselect
2
) applied to the gate of the second transistor can be selected so that the voltage passed to the floating gate storage transistor will not result in a program disturb condition.
REFERENCES:
patent: 5706240 (1998-01-01), Fiocchi et al.
patent: 5914514 (1999-06-01), Dejenfelt
Horch Andrew
Rowlandson Michael
Fliesler Dubb Meyer & Lovejoy LLP
Hoang Huan
Lattice Semiconductor Corporation
LandOfFree
Non-volatile memory element having a cascoded transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory element having a cascoded transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory element having a cascoded transistor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3134691