Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-04-06
2002-12-03
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185330
Reexamination Certificate
active
06490202
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memories and in particular the present invention relates to erase operations in a non-volatile memory device.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. There are several different types of memory. One type of memory is random access memory (RAM) that is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. Computers often contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in a row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into erasable blocks. Each of the memory cells can be electrically programmed on a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
To program a memory cell, a high positive voltage Vg is applied to the control gate of the cell. In addition, a moderate positive voltage is applied to the drain (Vd) and the source voltage (Vs) and the substrate voltage (Vsub) are at ground level. These conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to reduce the effective threshold voltage of the cell as compared to a cell that has not been programmed.
In flash memories, blocks of memory cells are erased as in groups. This is achieved by putting a negative voltage on the wordlines of an entire block and coupling the source connection of the entire block to Vcc (power supply), or higher. This creates a field that removes electrons from the floating gates of the memory elements. In an erased state, the memory cells can be activated using a lower control gate voltage.
A common problem with flash memory cells is over-erasure. A cell that is erased past a certain point becomes depleted and cannot be fully turned off. That is, too many electrons are removed from the floating gate, and the memory cell floating gate voltage becomes more positive than the threshold of the cell. The cell, therefore, cannot be turned off even if the control gate is at a ground potential. An over-erased memory cell can cause all memory cells coupled to the same column to be read as erased cells, even though they may be programmed.
In current flash memory cells, a pre-program cycle is performed on the block of memory cells prior to performing an erase cycle. As such, all the cells in a block are first programmed. The cells are then erased until all the cells are completely erased. A threshold voltage (Vt) distribution tightening operation is performed following the erase operation to recover memory cells that are over erased. As flash memory devices increase in memory cell density, the time needed to perform a complete erase operation also increases.
In flash memories, a substantial part of the erase cycle time is spent on the erase cycle. Out of a typical 1-second erase operation, about one-half of the time is spent on pre-programming the memory cells, and the other half is used on the erase cycle. An erase pulse requires about 10 ms, while an erase verification operation requires less than 1 &mgr;s. With the density of flash memories increasing, the total time to verify all the locations is becoming a substantial part of the cycle. For instance, in a 64 Megabit flash device organized in 16 erasable blocks, there are four million locations that need to be verified during an erase operation. A typical 1 &mgr;s time for each verify cycle results in a verify time of 4 seconds. Further, memory cells are being verified for levels that are much tighter than their regular read levels. Thus, they need to be sensed much slower. For instance, a normal read is verifying that an erased cell has a threshold level (Vt) that is less than 4.5V. During erase verification, the memory verifies that the cell has a Vt that is less than 3V. This margin is smaller than prior memories and is more susceptible to noise.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory with an improved process for erasing and verifying memory cells.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile memory device comprises an array of non-volatile memory cells arranged in erasable blocks, and an erase register associated with the erasable blocks. The erase register is configured to store data indicating an erase state of each of the erasable blocks.
In another embodiment, a non-volatile flash memory device comprises an array of non-volatile memory cells arranged in erasable blocks, where each erasable block comprises a plurality of addressable sub-blocks, and an erase register to store a plurality of data bits. Each of the plurality of data bits is associated with one of the sub-blocks. A control circuit is provided to perform erase operations on the plurality of addressable sub-blocks in response to a data state of the plurality of data bits.
In yet another embodiment, a non-volatile flash memory device comprises an array of non-volatile memory cells arranged in erasable blocks, where each erasable block comprises four sub-blocks. A volatile erase register comprising four data bits is provided. Each of the four data bits is associated with one of the four sub-blocks. A control circuit performs erase operations on the four sub-blocks in response to a data state of the plurality of data bits. The control circuit further performs an erase verification operation on the four sub-blocks and programs the four data bits in response to the erase verification operation.
A method of erasing a non-volatile memory device is provided. The method comprises applying an erase pulse to a block of addressable memory cells, performing an erase verification operation on the block of addressable memory cells to determine if the block of addressable memory cells has been erased, and programming an erase register in response to the verification operation.
A method of erasing a flash memory comprises performing a pre-program operation on a plurality of sub-blocks of a block of memory cells, applying a first series of erase pulses to the block of memory cells, performing an erase verification operation on the plurality of sub-blocks and programming an erase register having register bits. Each of the register bits corresponds to one of the plurality of sub-blocks and is pre-programmed to a first data state. The register bits are programmed to a second data state in r
Bolvin Kenneth W.
Leffert Jay & Polglaze P.A.
Tran M.
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