Non-volatile memory device with configurable row redundancy

Details Non-volatile memory device with configurable row redundancy Non-volatile memory device with configurable row redundancy

2001-02-14

2002-07-09

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S200000

Reexamination Certificate

active

06418051

ABSTRACT:

TECHNICAL FIELD
This invention relates to a non-volatile memory device with configurable row redundancy.
The invention relates, particularly but not exclusively, to semiconductor non-volatile memory devices which are electrically programmable and fabricated with CMOS technology, and the following description is made with reference to this field of application for convenience of explanation only.
BACKGROUND OF THE INVENTION
As it is well known, a semiconductor non-volatile memory device of the so-called “multimegabit” type, such as EEPROMs or Flash EPROMs, basically comprises a matrix of memory cells which accounts for a good proportion of the device area, specifically 40 to 70% of its total area.
The applications of such memory devices impose perfect performance of all the memory cells in the matrix during the device operation phases (reading, programming, erasing). In principle, the presence of at least one inoperative memory cell, commonly defined as “bit-fail”, is sufficient to put the whole device out of use.
This requisite for utmost reliability of the memory device taxes the manufacture of this type of integrated device, because a generic memory cell in a batch has a not null probability of turning up defective. In particular, the main causes of bit-fails are connected to the technological process used to fabricate the integrated device, e.g., conductive layers shorted together, variations in the process parameters, breakdown of dielectric layers, and so on.
Lacking arrangements to detect and correct bit-fails, the percentage of devices with properly performing memory cells in a chosen fabricating batch would be low to qualify for mass production methods. This percentage shows the so called prime yield of the fabricating batch and plays a very important role in the whole manufacturing process.
In memory devices, this yield is actually dependent on the faultiness spread not only through the cell matrix interior, but also through ancillary circuits to such matrix. However, in consideration of the large area occupied by the memory, the reduced yield in devices of this type is mainly due to faults occurring within the matrix.
Suitable circuit arrangements for the detection and the correction of bit-fail are therefore employed to increase the yield in integrated memory devices.
According to a commonly used technique, spare memory cells are provided to replace those cells which have been found faulty in the matrix.
These spare memory cells, usually called redundant, are identical to the matrix memory cells they have to replace, and are suitably controlled by dedicated control circuits added to the standard device circuitry.
In particular, the memory layout prompts the use of entire redundant cell rows or columns, so that corresponding rows or columns of the memory matrix can be replaced even on the occurrence of only one bit-fail therein. In this way, a good compromise can be made between fault-correcting capability and the requested area to perform redundancy control circuits.
The choice of the type of layout of redundant cells for use in a memory device, e.g., row redundancy or column redundancy, or both, is essentially tied to the knowledge of the distribution and typology of the faults appearing in the matrix for a given technological integration process.
Moreover, the yield of a silicon integration process is not constant over time, since it is dependent on the actions performed to improve both the process characteristics and the circuit functional aspects. Typically, the yield is comparatively low at the start of the manufacturing process, to then improve as the production volume increases following to the process optimizing actions.
For example, with a well developed integration technology widely employed for mass production, the yield may attain its highest possible levels.
Of course, it is important to keep the manufacturing yield in memory devices high, possibly also from the very start of the manufacturing process.
In addition, every increase of the corrective capability of a redundancy architecture associated with a matrix of memory cells provokes an increase of the required area for its control circuitry, as well as an increase of the weight of the whole device complexity.
This added complexity becomes a serious problem with the row redundancy techniques, which heavily penalize, moreover, the access time to a memory word.
Thus, prior approaches provide optimal designed architectures for a given degree of the corrective capability, which degree is, therefore, fixed and unvaried for all the devices being manufactured.
In practice, implementing specific solutions with a high corrective capability involves an unacceptable longer time for accessing memory words, besides an increase in silicon area occupation, because of the complex control arrangements required.
One prior architecture aimed to reduced the access time of high corrective capability solutions making use of redundant rows is schematically shown in FIG.
1
.
Particularly, the architecture
1
comprises a matrix
2
, called matrix sector, of memory cells which are organized into regular rows and columns, a row decoder block
3
, and a column decoder block
4
, as well as a read block
5
.
The read block
5
comprises basically read circuits (sense amplifiers) and output buffers.
The architecture
1
further comprises at least one matrix
6
of redundant cells, called redundancy sector, operative to correct bit-fails spread with equal probability over all the sectors of matrix
2
.
The architecture
1
finally comprises a memory
7
of the UPROM (Unreasonable Programmable Read-Only Memory) type for row redundancy.
It should be considered that in a flash memory device, there are usually many sectors of memory cells having predetermined capacity. In fact the storage capacity of the sectors can be constant for all sectors or vary between sectors.
This organization in sectors allows each cell matrix to be accessed separately for read, program and erase operations. In particular, whereas a program operation is selective of byte/memory words for any memory sector, an erase operation is shared by all the cells of each selected sector.
Selective access to the sectors is, therefore, achieved by providing a row or a column type of organization of the sectors themselves and a physical separation of the source lines of each sector.
In particular, with a by-row organization, the columns are distributed among all the sectors, and the selection takes place by row address, whereas in a dual manner, with a by-column organization, the rows are distributed among all the sectors and the selection takes place by column address.
Furthermore, the by-row or by-column organization of the matrix sectors can be performed by using single or double silicon level technologies. With a by-row organization, rows shared by the sectors are realized in low-resistivity polysilicon, whereas the columns are realized in metal, while with a by-column organization, a second metal level can be used to lower the overall resistance of the polysilicon rows, superposing the metal layer in contact with the polysilicon rows.
In processes with at least two metal levels, the matrix sectors can be organized in a combined by-row and by-column way. In this case, the row (column) decoding can use a hierarchic organization based on “global” rows (columns), or rows shared by all the sectors to which the local rows (columns) of the individual sectors are connected. The local rows (columns) are particularly enabled only for a selected sector.
A hierarchic organization of this type (by the rows or the columns) has a major advantage in that the effects of electric noise on the shared lines between adjoining cells under the different operating conditions are reduced, since the local bit lines or local word lines are shared by the cells of the single sectors.
By using a technological process with at least three metal levels, hierarchic decoding at the same time of the row and of the column is made feasible. In fact, in such a process, the global rows are realized with a

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