Non-volatile memory device which supplies erasable voltage to a

Details Non-volatile memory device which supplies erasable voltage to a Non-volatile memory device which supplies erasable voltage to a

1997-05-09

1998-07-28

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518523, 36518529, 36518533, 365218, G11C 1134

Patent

active

057870373

ABSTRACT:
In a nonvolatile semiconductor memory device comprising an address driving section comprising an N-channel transistor (11) and a P-channel transistor (12) and a memory cell (15) for erasing stored contents therefrom by supplying a control gate (CG) with a predetermined voltage, a negative voltage generation circuit (25) supplies a negative voltage to one of source and drain of the N-channel transistor (11) on erasing the stored contents in order to supply the negative voltage to the control gate (CG) of the memory cell (15) via the N-channel transistor (11), thereby erasing the stored contents from the memory cell (15). On writing data in the memory cell (15), a positive voltage generation circuit (30) supplies the control gate (CG) of the memory cell (15) with a higher voltage than an output voltage of an address driving section (10, 11, 12) in place of the output voltage of the address driving section.

REFERENCES:
patent: 5357465 (1994-10-01), Challa
patent: 5559736 (1996-09-01), Matsukawa et al.
patent: 5598369 (1997-01-01), Chen et al.

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