Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-04-06
2002-04-23
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S185140
Reexamination Certificate
active
06377507
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved non-volatile integrated circuit memory device with separate sense and store circuits to achieve high speed page mode operations, such as read or program.
2. Description of the Prior Art
Semiconductor integrated memory circuit devices for storing data typically have been categorized as either volatile, in which the data is lost once the power is turned off, or non-volatile, in which the data is retained even after the power is turned off.
Non-volatile memories, comprising an array of non-volatile memory cells arranged in a plurality of rows and columns (or bit lines), can be categorized as either NAND or NOR type, referring to the manner in which the non-volatile memory cells are arranged in the array. Further, the non-volatile memory cells can be arranged to operate in a page mode manner, in which a page of data (typically 512 bytes) is stored in a plurality of latches (or plurality of page buffers) that are integrated with the memory circuit device. Reading of the integrated memory circuit device causes data from a page of the memory cells to be read and stored in the plurality of latches. Thereafter the contents of the plurality of latches are read, typically, in a serial manner, from the integrated memory circuit device. Programming of the integrated memory circuit device causes data from the external to be stored in the plurality of latches. Thereafter, the contents of the plurality of latches are stored in a page of non-volatile memory cells. Typically a page of non-volatile memory cells lie in the same row or word line.
In a conventional page-mode read operation, whenever a word line is addressed, a wait state is necessary for the on-chip control circuits to sense out data stored in the memory cells of that selected word line. After being sensed out, the data is latched into the plurality of page buffers before they are clocked out to the I/O pads. This wait-state, typically around several micro-seconds, accounts for a significant portion of the average page-mode read access time. Especially in applications of reading large volume data, several consecutive word lines are often addressed successively. With one wait-state for each addressed word line, the overall read performance is deteriorated. Therefore, a non-volatile memory with minimized number of wait-states is needed to provide high performance page-mode read operation.
In the prior art, one of the factors causing the wait state is due to the sensing circuit and the latching circuit being provided together for sensing and latching the contents of memory cells along a bit line or a group of bit lines. Thus, the pitch attendant to each sensing circuit and accompanying latch circuit must be the same and must be small to accommodate the pitch of the corresponding bit line or group of bit lines.
In U.S. Pat. No. 5,768,215 a proposed solution to the aforementioned problem of the wait state is to provide two groups of page buffers, with each group of page buffers being one half the size of a page of memory cells. Initially, the data from a first page of memory cells is read into the two groups of page buffers. Thereafter, a first group of page buffers is read and the contents outputted to the external. However, as soon as the reading of the contents of the second group of page buffers commences, the reading of a second page of memory cells commences with the data read from one half of the second page of memory cells being stored in the first group of page buffers. After the contents of the second group of page buffers is outputted to the external, one half of the second page of memory cells will also have been read and stored in the first group of page buffers. As the reading of the first group of page buffers commences, the reading of the second half of the second page of memory cells commences and is stored in the second group of page buffers. This alternation of reading one half of a page of memory cells and storing the data into one of the groups of page buffers, while the contents of the other group of page buffers is read out continues. While this technique can avoid a certain amount of the wait time, it does not eliminate all.
In a conventional page-mode program operation, data is first loaded into the plurality of page buffers sequentially. Regardless of the number of bits (or collective bytes) to be programmed, all the data loaded into the plurality of page buffers will be programmed into the memory cells of a selected page simultaneously. Since the on-chip circuits, such as the charge pump (because typically programming requires a voltage source higher than the externally supplied voltage) can deliver only a limited amount of current, the efficiency of programming will deteriorate as the number of bits increases. Because of the limitation in the amount of current that can be provided by the on-board charge pump, one solution is to require a larger amount of time to program a page (or more) of data. Therefore a new technique is needed to provide high efficiency programming.
Non-volatile memory cells used in NAND architecture are typically of the stack gate type, such as that disclosed in U.S. Pat. No. 5,768,215. Further, the non-volatile memory cells used in NOR architecture can be both the stack gate type or the split gate type such as that disclosed in U.S. Pat. No. 5,668,757, whose disclosure is incorporated by reference in its entirety.
Finally, in the prior art, a combination sense amplifier and latch has been used to sense the content of the non-volatile memory cell, with the latch used to store the content from the sense amplifier or from the external, in a page mode operation. This, however, necessitates the combination sense amplifier/latch to have a pitch which is consistent with the pitch of the memory cells, which is a compromise in the performance of the sense amplifier.
SUMMARY OF THE INVENTION
It is an object of the present work to provide a nonvolatile semiconductor memory capable of performing high-speed page-mode read and program operation.
It is another object of the present work to provide a multi-level nonvolatile semiconductor memory product capable of performing high-speed page-mode read and program operation.
To achieve objects of the present work, a quick current level translator (QCLT) is designed to work with the conventional page latch. Each QCLT is a current-mode analog-to-digital converter (ADC) designed to detect the cell current and to convert it to binary codes. The codes are temporarily stored in Q-latches of QCLT and then transferred to page latches for clocking out. Each QCLT is shared among 32 bit lines. This results in a large pitch width which results in a high speed ADC. Furthermore, the QCLT could also be modified for multi-level cell current sensing. Since QCLT is a current-mode ADC, it could be used to resolve the cell current of a multi-level cell. Cell current will be converted to binary codes according to its signal magnitude.
The present invention is also capable of performing gapless read.
REFERENCES:
patent: 5535167 (1996-07-01), Hazani
patent: 5625590 (1997-04-01), Choi et al.
patent: 5963475 (1999-10-01), Choi et al.
Gray Cary Ware & Friedenrich LLP
Integrated Memory Technologies, Inc.
Phung Anh
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