Non-volatile memory device and erasing method therefor

Details Non-volatile memory device and erasing method therefor Non-volatile memory device and erasing method therefor

2007-09-04

2007-09-04

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185300

Reexamination Certificate

active

11215889

ABSTRACT:
During an erasing sequence, after a preprogram operation (S1), an erasing operation (S3), and an APDE operation (S5) are executed and confirmation by an APDE verify operation (S6: P) and confirmation by an erase-verify operation (S7: P) are completed, step A is executed prior to a soft-program operation (S10) of a plurality of memory cells. A dummy memory cell program operation (S8) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S9). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S11) can be prevented, and excessive soft-programming can be avoided.

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