1978-11-09
1980-03-11
Davie, James W.
357 54, 357 89, H01L 2978
Patent
active
041930800
ABSTRACT:
The present invention provides a memory device of MNOS FET type wherein a high concentration part and a low concentration part contact each other in the source region and the drain region, and further, double layered insulation films under the gate electrode extending across the source region and drain region are made to contact only the lower concentration part, so that an acceptor impurity is prevented from mixing into the double layered insulation films from the source region and drain region, thus greatly improving the life (number of repeated uses) of the device.
REFERENCES:
patent: 3709746 (1973-01-01), DeWitt
patent: 3853496 (1974-12-01), Kim
patent: 3959025 (1976-05-01), Polinsky
patent: 3986903 (1976-10-01), Watrous, Jr.
patent: 4011576 (1977-03-01), Uchida et al.
A. Platt et al., "FET Fabrication", IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, pp. 247-248.
Kambara Ginjiro
Koike Susumu
Matsuda Toshio
Davie James W.
Matsushita Electronics Corporation
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