Non-volatile memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S411000, C257S410000, C257S288000, C257S640000, C438S216000, C438S624000

Reexamination Certificate

active

06891271

ABSTRACT:
A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5663923 (1997-09-01), Baltar et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 6627491 (2003-09-01), Ebina et al.
patent: 20030054610 (2003-03-01), Ebina et al.
patent: 20030157767 (2003-08-01), Kasuya
patent: 20030166320 (2003-09-01), Kasuya
patent: 20030166321 (2003-09-01), Kasuya
patent: 20030166322 (2003-09-01), Kasuya
patent: 20030186505 (2003-10-01), Shibata
patent: 20030190805 (2003-10-01), Inoue
patent: 20030211691 (2003-11-01), Ueda
patent: 7-161851 (1995-06-01), None
patent: 2978477 (1999-09-01), None
patent: 2001-156188 (2001-06-01), None
U.S. Appl. No. 10/244,623, filed Sep. 17, 2002, Ebina et al.
U.S. Appl. No. 10/052,549, filed Jan. 23, 2002, Ebina et al.
U.S. Appl. No. 10/234,197, filed Sep. 5, 2002, Ebina et al.
U.S. Appl. No. 10/052,255, filed Jan. 23, 2002, Ebina et al.
Hayashi, Yutaka et al., “Twin MONOS Cell with Dual Control Gates,” 2000 IEEE VLSI Technology Digest.
Chang, Kuo-Tung et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Chen, Wei-Ming et al., “A Novel Flash Memory Device withS Plit Gate Source Sidelnjection and ONO Charge Storage Stack (SPIN),” 1997 VLSI Technology Digest, pp. 63-64.
U.S. Appl. No. 10/636,562, filed Aug. 8, 2003, Inoue.
U.S. Appl. No. 10/636,581, filed Aug. 8, 2003, Yamamukai.
U.S. Appl. No. 10/636,582, filed Aug. 8, 2003, Inoue.
U.S. Appl. No. 10/614,985, filed Jul. 9, 2003, Inoue.
U.S. Appl. No. 10/689,993, filed Oct. 22, 2003, Kasuya.
U.S. Appl. No. 10/689,987, filed Oct. 22, 2003, Kasuya.
U.S. Appl. No. 10/689,990, filed Oct. 22. 2003, Kasuya.
U.S. Appl. No. 10/690,025, filed Oct. 22, 2003, Kasuya.

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