Non-volatile memory device

Details Non-volatile memory device Non-volatile memory device

2002-04-16

2004-07-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185030

Reexamination Certificate

active

06768681

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, more particularly, to a method of fabricating an oxide-nitride-oxide ONO electrically erasable and programmable read only memory EEPROM device having two transistors for performing two bit operations, and a method of driving the ONO EEPROM device.
2. Description of Related Art
An ONO EEPROM device is one type of non-volatile semiconductor memory device and has an oxide-nitride-oxide (ONO) layer in the bottom of a gate. The nitride layer in the ONO EEPROM device is a dielectric layer trapping or de-trapping electrons for data programming, data erasing, and data readout in a memory cell.
Generally, the ONO EEPROM device applies a Fowler-Nordheim (F-N) tunneling phenomenon or channel hot electron injection (CHEI) to trap electrons. The F-N tunneling method consumes less current to trap electrons, but has longer trapping time. In contrast, the CHEI method has shorter trapping time, but consumes more current to trap electrons so that the number of electron-trapping cells is limited.
U.S. Pat. No. 5,768,192 discloses an ONO non-volatile memory device applying the CHEI method to trap electrons in the nitride layer.
FIG. 1
a
illustrates a cross sectional configuration for a unit cell of a conventional ONO EEPROM device applying a CHEI method to write a data, that is, to program a data.
FIG. 1
b
shows an equivalent circuit diagram for the unit cell of the conventional ONO EEPROM device.
Referring to
FIG. 1
a
and
FIG. 1
b
, the unit cell of the conventional ONO EEPROM device
10
comprises a cell transistor CT
11
having a conductive gate
30
connected to a word line WL
11
and source/drain junction areas
41
and
42
connected to a pair of bit lines BL
11
and BL
12
, respectively.
The conventional ONO EEPROM device comprises a trapping dielectric layer
25
with the ONO structure stacking serially a bottom oxide layer
21
, a nitride layer
22
, and a top oxide layer
23
on a silicon substrate of a first conductive type, for example, on a channel area
43
of a p-type silicon substrate
20
.
The conductive gate
30
connected to the word line WL
11
is formed on the trapping dielectric layer
25
. The source/drain junction areas
41
and
42
are formed on the silicon substrate
20
, below both sides of the conductive gate
30
, and are overlapped with the conductive gate
30
.
The bottom oxide layer
21
of the trapping dielectric layer
25
is an electric isolation layer for the channel area
43
and the top oxide layer
23
is an electric isolation layer for the word line WL
11
. The nitride layer
22
between the bottom oxide layer
21
and the top oxide layer
23
is an electron-trapping layer for data retention.
The above described conventional EEPROM device applies pre-determined voltages to the conductive gate
30
and to a pair of bit lines, BL
11
and BL
12
, connected to the source/drain junction areas
41
and
42
, respectively. Therefore, the electrons in the channel layer are trapped on the nitride layer
22
so that data is written in a corresponding memory cell.
The conventional EEPROM device applies the CHEI method to program data to a memory cell. The CHEI method requires a considerable amount of current for writing data to numerous memory cells. Therefore, a confined amount of current also limits the number of memory cells for writing data.
In addition, excessive electron de-trapping in an electron-trapping layer generates disturbance phenomena for erasing data in a memory cell when the data in the memory cell of the conventional EEPROM device is erased, which results in lowering device reliability of the conventional EEPROM device.
SUMMARY OF THE INVENTION
To overcome the above-described problems in conventional technology, the present invention provides a fabricating method of an ONO EEPROM device improving electron trapping efficiency and reducing trapping current, and a method of driving the ONO EEPROM device thereof.
Another purpose of the present invention is to provide a fabricating method of an ONO EEPROM device employing a split word line to improve electron-trapping efficiency in the CHEI method, and a method of driving the ONO EEPROM device thereof.
Another purpose of the present invention is to provide a fabricating and driving method of an EEPROM device employing a split word line with an ONO dielectric layer to form two memory cells between a pair of bit lines, and thereby improve integration degree of the EEPROM device.
Another purpose of the present invention is to provide a fabricating and driving method of an EEPROM device preventing disturbance phenomena from erasing data to improve reliability of the EEPROM device.
Another purpose of the present invention is to provide a fabricating and driving method of an ONO EEPROM device having two transistor cells between a pair of bit lines, and employing each of the transistor cells as a selection transistor cell to improve disturbance immunity of the EEPROM device.
Another purpose of the present invention is to provide a fabricating and driving method of an ONO EEPROM device applying a self-align method to generate a split word line, thereby reducing cell size.
The present invention is directed to a non-volatile memory device which includes a silicon substrate of a first conductivity type having first and second channel areas adjacent each other. First and second conductive gates are formed on the first and the second channel areas facing each other. First and second insulation layers are formed on the bottoms of the first and the second conductive gate, and on the silicon substrate between the first and the second conductive gate. First and second junction areas of a second conductivity type are formed in the silicon substrate overlapping with the first and the second conductive gate, wherein the first and the second channel areas are defined as a space between the first and the second junction areas.
In one embodiment, the first conductive gate is a control gate and the second conductive gate is a selection gate. Alternatively, the first conductive gate is a selection gate and the second conductive gate is a control gate.
The first and the second insulation layers can include ONO layers including a nitride layer between oxide layers as an electron trapping layer.
The portion of the ONO layers formed in the bottom of the first and the second conductive gates functions as dielectric layers for trapping electrons, and the portion of the ONO layers formed between the first and the second conductive gates functions as an insulation layer.
The present invention is also directed to a non-volatile memory device comprising: a silicon substrate of a first conductivity type including first and second channel areas adjacent each other; first and second conductive gates formed on the first and the second channel areas, respectively, facing each other; first and second, including electron trapping layers, formed in the bottom of the first and the second conductive gates, and on the silicon substrate between the first and the second conductive gates; and first and second junction areas of a second conductivity type formed in the silicon substrate overlapping with the first and the second conductive gates, wherein the first and the second channel areas are defined as a space between the first and the second junction areas, the non-volatile memory device uses one of the conductive gates as a selection gate while the other of the conductive gates functions as a control gate so that the conductive gates are driven independently from each other, and applies an electric field to the control gate to trap electrons of a channel area in the bottom of the selection gate to the electron trapping layer of the dielectric layers in the bottom of the control gate so that each bit data is respectively stored in each of the dielectric layers.
The present invention is also directed to a non-volatile memory device comprising: a pair of bit lines; a pair of word lines; and a unit cell having first

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