Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2011-04-05
2011-04-05
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185040, C365S185180
Reexamination Certificate
active
07920423
ABSTRACT:
A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.
REFERENCES:
patent: 4037242 (1977-07-01), Gosney
patent: 5068622 (1991-11-01), Mead et al.
patent: 5197028 (1993-03-01), Nakai
patent: 5450363 (1995-09-01), Christopherson et al.
patent: 5515317 (1996-05-01), Wells et al.
patent: 5574879 (1996-11-01), Wells et al.
patent: 5666307 (1997-09-01), Chang
patent: 5787038 (1998-07-01), Park
patent: 5796656 (1998-08-01), Kowshik et al.
patent: 5825063 (1998-10-01), Diorio et al.
patent: 5864569 (1999-01-01), Roohparvar
patent: 5898613 (1999-04-01), Diorio et al.
patent: 6002623 (1999-12-01), Stave et al.
patent: 6097637 (2000-08-01), Bauer et al.
patent: 6137153 (2000-10-01), Le et al.
patent: 6233717 (2001-05-01), Choi
patent: 6353568 (2002-03-01), Sung
patent: 6363008 (2002-03-01), Wong
patent: 6522584 (2003-02-01), Chen et al.
patent: 6549457 (2003-04-01), Srinivasan et al.
patent: 6558967 (2003-05-01), Wong
patent: 6654286 (2003-11-01), Kawakami
patent: 6693829 (2004-02-01), Babudri et al.
patent: 6845039 (2005-01-01), Chen et al.
patent: 6845044 (2005-01-01), Horch et al.
patent: 6870767 (2005-03-01), Rudelic et al.
patent: 6950342 (2005-09-01), Lindhorst et al.
patent: 6999887 (2006-02-01), Rehm et al.
patent: 7032064 (2006-04-01), Barnett et al.
patent: 7057935 (2006-06-01), Chevallier
patent: 7272041 (2007-09-01), Rahman et al.
patent: 7283390 (2007-10-01), Pesavento
patent: 2004/0004861 (2004-01-01), Srinivas et al.
patent: 2006/0071793 (2006-04-01), Pesavento
patent: 2006/0221715 (2006-10-01), Ma et al.
patent: 2007/0229230 (2007-10-01), Drago et al.
Ma, Yanjun et al., “Reliability of pFET EEPROM With 70-Å Tunnel Oxide Manufactured in Generic Logic CMOS Processes”, IEEE Transactions on Device and Materials Reliability, vol. 4, No. 3, pp. 353-358, Sep. 2004.
Ma Yanjun
Mozsgai Steven I.
Fenwick & West LLP
Hoang Huan
Synopsys Inc.
LandOfFree
Non volatile memory circuit with tailored reliability does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non volatile memory circuit with tailored reliability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non volatile memory circuit with tailored reliability will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2720316