Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-11-28
2002-08-13
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185280
Reexamination Certificate
active
06434051
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a non-volatile memory circuit with a floating gate, and more particularly to a non-volatile memory circuit that can directly read the floating gate voltage of a storage transistor with a floating gate.
BACKGROUND ART
Non-volatile memory that uses transistors with floating cells in memory cells can store data even after the power is turned off and can be used in various aspects.
Conventional non-volatile memory circuits write (program) data by injecting a charge into the floating gate of a memory cell transistor to increase its threshold voltage, and delete data by extracting the charge from the floating gate to lower the threshold voltage. Data is ‘
0
’ when the threshold voltage is high and ‘
1
’ when the threshold voltage is low, and binary data is stored in the memory cell.
When such binary data is to be read, a prescribed read voltage is applied to a control gate of a memory cell transistor and the value of the current flowing through that transistor in accordance with the threshold voltage at that time is detected. Here, a reference voltage, which is between the two threshold voltages described above, is applied to the gate of a reference transistor and the current from the above memory cell transistor and the reference current from the reference transistor are compared.
Write (program) and erase operations can also be implemented by using the reference current from such a reference transistor. That is, when data is being written, a charge is injected into the floating gate until the value of the current from the memory cell transistor becomes smaller than the reference current. When data is being erased, charge is extracted from the floating gate until the value of the current from the memory cell transistor becomes greater than the reference current.
However, with the increasing capacity of information being stored in memory cells, the information being stored is tending to be multi-value or analog data. That is, when n-value data is to be stored in a memory cell, an n-stage charge injection level is set in the floating gate and the accompanying differences in n-stage threshold voltages must be read.
In the method wherein the current from a conventional memory cell transistor is compared with the current from a reference transistor, it is difficult to read information stored as multi-value or analog information. This is because to read n-value stored information using conventional methods, n−1 type reference voltages must be applied to the reference transistor and the n−1 type reference currents must be compared only with the current from the storage transistor.
Thus, in the method wherein a charge is injected into and extracted from the floating gate of a memory cell transistor and the accumulated charge is read as the value of the current of the storage transistor that corresponds to the threshold voltage of the memory cell transistor, it is extremely difficult to cope with any future change to multi-value or analog data.
Therefore, an object of the present invention is to provide a non-volatile memory circuit that can easily read information from a storage transistor with a floating gate.
A further object of the present invention is to provide a non-volatile memory circuit that can easily write information to a storage transistor with a floating gate.
A still further object of the present invention is to provide a non-volatile memory circuit that can easily read information from a storage transistor with a floating gate that stores multi-value or analog data.
An even still further object of the present invention is to provide a non-volatile memory circuit that can easily write information to a storage transistor with a floating gate that stores multi-value or analog data.
Another further object of the present invention is to provide a non-volatile memory circuit that broadens the dynamic range that can be stored by a storage transistor with a floating gate.
DISCLOSURE OF THE INVENTION
In one view of the present invention, both a storage transistor with a floating gate and a feedback transistor with a floating gate are commonly connected at the source thereof and a load circuit is provided on the drain side of both transistors. A negative feedback circuit is provided between the drain of the storage transistor and the floating gate of the feedback transistor. An output transistor for amplification is a preferable example for the negative feedback circuit. Its gate is connected to the drain of the storage transistor and a voltage corresponding the gate voltage is generated at an output terminal. This output terminal and the floating gate of the feedback transistor are connected.
The memory circuit of such configuration operates so that the voltage corresponding the charge in the floating gate of the storage transistor and the output voltage of the output terminal become the same. Therefore, the voltage of the floating gate of the storage transistor can be directly detected at the output terminal. Accordingly, multi-value or analog information can be easily written to or read from the floating gate of the storage transistor. Similarly, information can be easily written or read when binary information has been stored.
To achieve the above objects, the non-volatile memory circuit in another view of the present invention comprises: a storage transistor with a storage floating gate; a feedback transistor with a feedback floating gate, commonly connected at a source with the above storage transistor; a load circuit connected to the storage transistor and the feedback transistor; an output transistor, having a gate connected to the drain of the storage transistor, for generating a voltage corresponding to the gate voltage at an output terminal and; a feedback path provided between the output terminal and the feedback floating gate.
REFERENCES:
patent: 5428571 (1995-06-01), Atsumi et al.
patent: 5521858 (1996-05-01), Shibata et al.
patent: 6111791 (2000-08-01), Ghilardelli
patent: 5-282881 (1993-10-01), None
patent: 9-265786 (1997-10-01), None
patent: 10228790 (1998-08-01), None
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Mai Son
LandOfFree
Non-volatile memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile memory circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2944496