Non-volatile memory cell with multiple resistive sense...

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S051000, C365S148000, C365S158000, C365S163000, C365S171000

Reexamination Certificate

active

07933136

ABSTRACT:
A non-volatile memory cell array and associated method of use. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.

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Giacomini, R. and Martino, J.A., “Modeling Silicon on Insulator MOS Transistors with Nonrectangular-Gate Layouts,” Journal of the Electrochemical Society, 2006, pp. G218-G222, vol. 153, No. 3.

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