Non-volatile memory cell with enhanced cell drive current

Details Non-volatile memory cell with enhanced cell drive current Non-volatile memory cell with enhanced cell drive current

2001-11-09

2003-02-04

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185280

Reexamination Certificate

active

06515899

ABSTRACT:

TECHNICAL FIELD
The invention relates to non-volatile memory and, more particularly, to a non-volatile memory cell with increased drive current.
BACKGROUND
Non-volatile memory devices, such as EPROM, EEPROM, and Flash EEPROM, store data even after power is turned off. One common application of EEPROMs is in programmable logic devices (PLDs). PLDs are standard semiconductor components purchased by systems manufacturers in a “blank” state that can be custom configured into a virtually unlimited number of specific logic functions. PLDs provide system designers with the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. PLDs may be reprogrammable, meaning that the logic configuration can be modified after the initial programming.
The manufacturing of PLDs has moved progressively toward defining smaller device features, characterized by the channel length of transistors. As feature sizes shrink, the conventional EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In most cases, cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry.
Typically, in programmable logic EEPROM devices, to store a logical zero, electrons are injected onto a floating gate of a transistor to provide a negative voltage on the floating gate. Having a negative charge on the floating gate increases the control gate threshold voltage needed to turn on the transistor. The injection of electrons is accomplished by forcing electrons to tunnel from the source/drain region through a tunnel oxide layer or “tunnel opening” to the floating gate. Conversely, to store a logical one, the floating gate is discharged and the threshold voltage is decreased by causing electrons on the floating gate to tunnel through the tunnel opening in the opposite direction to the source/drain region.
One example of a commercially successful EEPROM structure for programmable logic applications is shown in U.S. Pat. No. 4,924,278 (hereinafter “the '278 patent”), issued to Stewart Logie on May 8, 1990 and assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif.
FIGS. 1 and 2
show a schematic diagram and a cross-section, respectively, of one embodiment of the EEPROM structure shown in the '278 patent. The EEPROM structure uses a single layer of polycrystalline silicon and a control gate formed in the silicon substrate to eliminate the need to form a separate control gate and floating gate in layers of poly silicon. The EEPROM structure is made up of three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. In order to “program” the floating gate of the sense transistor, a net positive charge is placed on the gate by causing free electrons from the floating gate to tunnel into the source region of the write transistor through the tunnel opening. Likewise, to erase the floating gate, the floating gate is given a net negative charge by causing electrons to tunnel from the source region onto the floating gate through the tunnel opening.
FIG. 2
shows a standard EEPROM memory cell
10
. A P-type substrate
5
has N+ type regions formed on and below its surface by standard diffusion techniques. These N+ type regions correspond to the source and drain regions of the three transistors that make up the EEPROM memory circuit. Write transistor
20
comprises drain
22
, source
24
, channel region
25
, gate oxide layer
27
and control gate
28
. Sense transistor
30
comprises drain
32
, source
34
, channel region
35
, gate oxide layer
37
, and N-type polycrystalline silicon (poly-Si) floating gate
38
. Read transistor
40
comprises drain
41
, source
32
, which is also the drain of sense transistor
30
, channel region
45
, gate oxide layer
47
, and control gate
48
. Poly-Si floating gate
38
is capacitively coupled to source
24
of write transistor
20
via tunnel oxide layer
55
(approximately 90 .ANG. in thickness). Poly-Si floating gate
38
also extends over channel region
35
of sense transistor
30
so that when a sufficient positive charge is on poly-Si floating gate
38
, channel
35
will invert and conduct current between source
34
and drain
32
of sense transistor
30
.
Operation of the memory cell
10
will be described with reference to
FIGS. 1 and 2
. In
FIG. 1
, word line WL and WLR are connected to control gates
28
and
48
, respectively, of write transistor
20
and read transistor
40
. Tunnel oxide layer
55
(the tunnel opening) is represented by capacitor C
t
while gate oxide layer
37
between ACG
39
and poly-Si floating gate
38
is represented by capacitor C
g
. Drain and source contacts are represented by D and S, respectively.
The three operations of the memory circuit are write, erase, and read. The various voltages applied to the circuit of
FIG. 2
are shown in Table 1.
TABLE 1
WL
Write
Read
PTG
Substrate
Control
WLR
Read
V
cc
ground
V
sense
ground
ground
ground
V
cc
Pro-
V
pp
V
pp
HiZ
ground
ground
ground
ground
gram
Erase
V
cc
ground
HiZ
V
pp
ground
V
pp
V
cc
When N type poly-Si floating gate
38
is written upon, or programmed, the floating gate is given a positive charge by removing free electrons therefrom. To accomplish this, first, a high programming voltage V
pp
is applied to word line WL, which turns on write transistor
20
. By turning on transistor
20
, a write signal applied to drain
22
of write transistor
20
is coupled to source
24
. High programming voltage V
pp
is applied to drain
22
of write transistor
20
, while source
34
of sense transistor
30
, as well as drain
41
of read transistor
40
and substrate
5
, are grounded.
Because the capacitance between source
24
and floating gate
38
across tunnel oxide layer
55
is very small (on the order of 0.004 pF), and the capacitance between source
34
/
39
and floating gate
38
across gate oxide layer
37
is about ten times greater, a large percentage (on the order of 90%) of the voltage difference between source
24
and source
34
/
39
(i.e., V
pp
) appears between source
24
and floating gate
38
across tunnel oxide layer
55
. This voltage is sufficient to cause electron tunneling from floating gate
38
to source
24
of write transistor
20
through tunnel oxide layer
55
, resulting in a net positive charge on floating gate
38
. The positive charge is sufficient to turn on sense transistor
30
because floating gate
38
extends over channel region
35
of sense transistor
30
. This indicates a logical 1 since current can flow through sense transistor
30
during a read operation.
To erase floating gate
38
high programming voltage V
cc
is applied to word line WL and V
pp
to source
34
of sense transistor
30
/
39
, while drain
22
of write transistor
20
and substrate
5
are grounded. In this biasing arrangement, the high voltage at source
34
/
39
is capacitively coupled to floating gate
38
and almost all of high programming voltage V
pp
appears across tunnel oxide layer
55
between floating gate
38
and grounded source
24
. This causes electrons from source
24
to tunnel through tunnel oxide layer
55
, resulting in a net negative charge on floating gate
38
. Thus, channel
35
of sense transistor
30
is not inverted and sense transistor
30
is shut off.
The memory cell
10
of
FIGS. 1 and 2
has been reliably used for many years. Nonetheless, as is typical in the electronics industry, it is desirable to further increase speed and reduce the size of the memory cell. Unfortunately, as oxide thickness of transistors in the non-volatile memory cells are continually scaled down, such transistors are susceptible to the high voltages used in programming and erasing the cell. For example, in
FIG. 1
, when a high voltage is placed on PTG, this voltage is passed to node A, which correspondingly places a high vol

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