Non-volatile memory cell with BTBT programming

Details Non-volatile memory cell with BTBT programming Non-volatile memory cell with BTBT programming

2011-07-19

2011-07-19

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185100, C365S185050, C365S185260

Reexamination Certificate

active

07983093

ABSTRACT:
A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels.

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