Non-volatile memory cell techniques

Details Non-volatile memory cell techniques Non-volatile memory cell techniques

2006-01-24

2006-01-24

Phan, Trong (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280

Reexamination Certificate

active

06990020

ABSTRACT:
A non-volatile memory cell (10) includes a charge-storing node (16). An electrically insulating first layer (76) is coupled between the node and a source of a first voltage (22). An electrically insulating second layer (66) is coupled between the node and a source of a second voltage (20–21). The area of the first layer is smaller than the area of the second layer. A controller (90) is arranged to cause the first voltage to be greater than the second voltage so that charge is extracted from the node and is arranged to cause the second voltage to be greater than the first voltage so that charge is injected into the node.

REFERENCES:
patent: 4884239 (1989-11-01), Ono et al.
patent: 5818761 (1998-10-01), Onakado et al.
patent: 6215148 (2001-04-01), Eitan
patent: 6266278 (2001-07-01), Harari et al.
patent: 6631088 (2003-10-01), Ogura et al.
patent: 6687164 (2004-02-01), Matsuda et al.
patent: 6804149 (2004-10-01), Ogura et al.
Korotkov et al., Resonant Fowler-Nordheim Tunneling through Layered Tunnel Barriers and its Possible Applications, Techn. Dig. IDEM '99. pp. 223-226, State University of New York, USA.
Shukuri et al., CMOS Process Compatible ie-Flash (inverse gate electrode Flash) Technology for System-on-a Chip. IEEE 2001 Custom Integrated Circuits Conference, pp. 179-182. Central Research Laboratory, Hitachi Ltd., Japan.
Ohsaki et al., A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes, IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 311-316, Japan.
McPartland et al., 1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 158-161, Bell Laboratories, Lucent Technologies, USA.
Carman et al., Single Poly EEPROM for Smart Power IC's, ISPSO 2000, May 22-25, 2000 IEEE, pp. 177-179, France.
Chi et al., A New Single-poly Flash Memory Cell with Low-voltage and Low-power Operations for Embedded Applications, MS E140, Advanced Technology Group, National Semiconductor Cor., pp. 126-127, USA.

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