Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-08-15
2006-08-15
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185140
Reexamination Certificate
active
07092293
ABSTRACT:
A configuration circuit includes a latch and a dedicated non-volatile memory cell. The non-volatile memory cell is initially programmed or erased. The latch is then set to store a first logic value by coupling the latch to a first voltage supply terminal in response to an activated control signal. When the control signal is de-activated, the latch is de-coupled from the first voltage supply terminal and coupled to the non-volatile memory cell. If the non-volatile memory cell is programmed, the latch is coupled to a second voltage supply terminal, thereby storing a second logic value in the latch. If the non-volatile memory cell is erased, the latch is isolated from the second voltage supply terminal, and the first logic value remains stored in the latch. The latch can also be directly written through one or more access transistors, thereby facilitating testing.
REFERENCES:
patent: 5548552 (1996-08-01), Madurawe
patent: 5572715 (1996-11-01), Gowni
patent: 5982683 (1999-11-01), Watson et al.
patent: 6172519 (2001-01-01), Chiang et al.
patent: 6243296 (2001-06-01), Sansbury
Paak Sunhom
Young Phillip A.
Elms Richard
Hoffman E. Eric
Liu Justin
Nguyen Hien N
Xilinx , Inc.
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