Non-volatile memory cell for linear mos integrated circuits...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S096000, C365S104000

Reexamination Certificate

active

06229733

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
This invention relates generally to non-volatile memory cells and, more particularly, to a non-volatile memory cell for a linear metal oxide semiconductor (MOS) integrated circuit.
Precision performance by a linear MOS integrated circuit is typically accomplished by internally trimming the circuit currents and voltages. Conventional trimming techniques are performed as part of the manufacturing process and must be permanent so that the trimming does not change when power is removed from the circuit. Several techniques use a fuse-based technology, such as the metal spike shorting of the emitter-base junction of a NPN transistor, or the opening of metal or thin film links, that require high current pulses to sever the subject material. Another method requires specialized equipment for the laser trimming of thin film links or the vernier trim of thin film resistor tabs, which may drift over time. All of these techniques are intended for low-density memory applications. High-density storage techniques use either “anti-fuse” technology or place a long-term charge storage on the MOSFET gates. These techniques, however, add complex processing steps to wafer fabrication and extra cost to the device.
What is needed, therefore, is an inexpensive and user-programmable technique for performing a parametric trim of a linear MOS integrated circuit.
BRIEF SUMMARY OF THE INVENTION
In accordance with the invention, a non-volatile memory cell comprises a metal oxide semiconductor field effect transistor (MOSFET) fabricated to read back a logic level “one” state and programmable by a gate to drain fusing to read back to a logic level “zero” state. The MOSFET drain has a blunted and notched “V” shape to enhance the formation of a localized hot spot during lateral NPN transistor snapback for a controlled meltdown of gate oxide and the creation of an ohmic gate to drain path. The MOSFET gate oxide is also made thick enough to achieve snapback upon application of a gate bias voltage without gate oxide rupture.
A metal oxide semiconductor (MOS) integrated circuit typically includes a plurality of memory cells composing a programmable array. The MOSFET drains of each memory cell are tied together in parallel and connected to a high-level programming voltage, and the MOSFET sources are tied to ground. Each memory cell may further comprise a series pair of switches connecting a low-level bias voltage to the MOSFET gate for cell programming based on “snapback selectivity” and connecting a bias current to the MOSFET gate for cell read-back, and a parallel pair of switches shunting the gate to the source to inhibit cell programming. The array may be user-programmed to selectively engage parametric elements distributed throughout a linear MOS integrated circuit and thereby accomplish a parametric trim of the circuit for precision performance in an intended application.


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