Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-02-14
2001-06-05
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185260
Reexamination Certificate
active
06243298
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor memory devices, and in particular to a non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions.
Non-volatile semiconductor memory devices retain stored information even when the applied power is removed from the devices. There are various types of non-volatile semiconductor memory devices. These include read-only-memory (ROM) wherein by implanting P-type dopants such as Boron or N-type dopants such as Phosphorous into the channel region of the memory cell the state of the cell is permanently programmed to “0” or “1”. Another type of non-volatile memory uses programmable fuses wherein an electrical signal is applied to the fuse to blow the fuse resulting in an open circuit, or the fuse is kept intact for a short. There is also erasable programmable read-only-memory (EPROM) that typically uses channel hot electron (CHE) injection into a floating gate to change the threshold voltage of the memory cell to a high Vt state, and ultra-violate (UV) light to erase the cell back to its original low Vt state. Electrically erasable programmable read-only-memory (EEPROM) uses the so called Fowler-Nordheim (FN) tunneling of electrons into or out of the floating gate under high electric field to program or erase the cell. Flash memory is yet another type of non-volatile memory. Several different types of flash memory cell structures have been developed, including split-gate source-side injection cell, triple Poly Poly-Poly erase cell , and stack gate cell.
FIG. 1
shows a prior art n-channel stack gate flash memory cell
9
. Memory cell
9
includes N+ source
12
and drain
13
regions spaced apart in a P-type silicon substrate
10
to form a channel region
11
. Source region
12
may be formed as a N+,N− double diffused junction for improved cell reliability, while drain region
13
remains N+ for maximum hot electron injection efficiency. A P+ region
20
, typically created by a halo implant, may be formed adjacent to drain region
13
to improve hot electron generation. A floating gate
15
of Polycrystalline silicon material is laid on top of a tunneling dielectric
14
, e.g. silicon dioxide, which overlaps the channel region
11
and parts of the source
12
and drain
13
regions. Stacked on top of floating gate
15
is a gate
19
of polycrystalline material upon an insulation dielectric combination of oxide
18
, nitride
17
and oxide
16
films.
FIG. 2
is the circuit symbol representing the cell structure described in FIG.
1
. There are several ways to program and erase the cell. To program stack gate cell
9
, one approach uses channel hot electron injection by applying a high voltage (e.g. 9V) to gate
19
, 0V to substrate
10
and source
12
, and 5V to drain
13
. Maintaining this biasing for about 2 &mgr;s is programs the threshold voltage of the cell from an initial state of Vt=1.4V to a program state of Vt=5.8V as described in a paper by Watanabe, H., et al., “Novel 0.44 &mgr;m
2
Ti-salicide STI Cell Technology for High-Density NOR Flash Memories and High Performance Embedded application” IEEE, IEDM Tech. Dig., 1998, pp. 975-978. Another approach uses channel initiated secondary electron injection (CISEI) by applying Vgs=Vds=−Vbs=3V for 1 ms during which the threshold voltage increases by 1.5 V, as described in a paper by Bude, J. D. et al., “EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing” IEEE, IEDM Tech. Dig., 1995, pp. 989-991.
To erase stack gate cell
9
, one approach uses the so called source-side erase by applying 12V to source
12
and 0V to gate
19
and substrate
10
, and floating drain
13
. In roughly 500 ms, the cell is erased from a high threshold voltage back to low threshold voltage, e.g., from 8V to 2V. In another approach, commonly referred to as negative gate source-side erase, 4V is applied to source
12
and −8V to gate
19
, 0V to substrate
10
, and drain
13
is left floating. In yet another approach −10V is applied to gate
19
and 6V to substrate
10
and the drain
13
and source
12
are left floating as described in a paper by Kim, J., et al., “A novel 4.6F
2
NOR Cell Technology with Lightly Doped Source (LDS) Junction For High Density Flash Memories” IEEE, IEDM Tech. Dig., 1998, pp. 979-982. Erase from the drain side causes hole injection into oxide which degrades programmability of the cell as well as the cycling characteristics of the cell, as described in a paper by Haddad, S., et al., IEEE Electron Device Letters, Vol., 10, No. 3, March 1989, pp. 117-119.
Conventionally, the initial cell threshold voltage Vt (i.e., the Vt after manufacturing of the memory and prior to the first program or erase operation), defined as the gate voltage of the cell at a certain drain current level (e.g., 1 nA), is set to a target level (e.g., 1.4V to 2V) by either a channel threshold enhancement implant or through a halo implant. However, as technology shrinks to smaller geometries and lower operating voltages, such high initial Vt's as 1.4V to 2V become a barrier to low VCC design. This is because at low VCC's, no cell current can be detected. Further, as described in paper of Bude, J. D. et al., “EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing” IEEE, IEDM Tech. Dig., 1995, pp. 989-991 and in U.S. Pat. Bude, 5,659,504, it is possible to use the cell for low VCC operation, but the programming time is in the mili-second range. This is at least two orders of magnitude higher than CHEI programming time.
Thus, it is advantageous to lower the initial threshold voltage Vt of the cell. However, lower initial threshold voltage can lead to subthreshold leakage.
FIG. 3
is used to illustrate the adverse effect of subthreshold leakage. In
FIG. 3
, memory cells are arranged in an array of plurality of rows of wordlines, WL
0
, WL
1
, . . . WL(2
m
−1) and columns of bitlines, BL
0
, BL
1
, BL
2
, . . . BL(2
n
−1), with all sourcelines connected together and a shared substrate as shown in FIG.
3
. In low Vcc operations (e.g., 3V), supplying a drain voltage of, for example 4V, to a selected bitline requires a charge pump circuit. Because of a charge pump's limited current supply capability and the low Vt of unprogrammed cells in the array of
FIG. 3
, subthreshold leakage through the unselected unprogrammed cells connected to the selected bit line causes the drain voltage applied to the selected bitline to be lowered. This results in longer programming time.
In the prior art array structures such as the one shown in
FIG. 3
, erase operation involves either source-side erase or negative gate erase. This type of erase operation erases either an entire block of cells that share the same sourceline, or specific cells that share the same row. In these schemes byte erase becomes impossible, a drawback which further limits the applications of the device.
There is therefore a need for an improved low VCC operational non-volatile memory cell.
SUMMARY OF THE INVENTION
In accordance with the present invention, a low VCC operational non-volatile memory cell includes a drain region and a source region separated by a channel region. A tunneling dielectric layer extends over the channel region and a portion of the drain and source regions. A floating gate extends over the tunneling dielectric. An insulating layer extends over the floating gate, and a control gate extends over the insulating layer.
In one embodiment, the channel region is implanted with a relatively low dosage of channel threshold enhancement impurities or halo impurities to obtain a low initial threshold voltage in the range of, for example, 0V to 0.8V. The low initial threshold voltage allows the target program threshold voltage to also be lower such that a programming margin of, e.g., 1V to 1.5V over VCC is sufficient. For example, for VCC=2.5V, the target program threshold voltage can be set to Vt
Lee Hsiao-Lun
Park Eung Joon
Pourkeramati Ali
Azalea Microelectronics Corporation
Le Thong
Nelms David
Townsend and Townsend / and Crew LLP
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