Non-volatile memory cell array with shared erase device

Details Non-volatile memory cell array with shared erase device Non-volatile memory cell array with shared erase device

2001-07-23

2002-10-01

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290

Reexamination Certificate

active

06459615

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to electronic memory devices, and more particularly to arrays of non-volatile memory cells for use in electronic memory devices such as electrically erasable programmable read-only memories (EEPROMs).
BACKGROUND OF THE INVENTION
A non-volatile memory device is capable of retaining stored information after disconnection of its power source. An EEPROM is a type of non-volatile memory device in which information is written to and erased from the memory cells thereof using an electrical signal. EEPROMs are often implemented as “flash” memory devices in which all memory cells or designated sectors of cells can be simultaneously erased. Such devices typically utilize floating gate transistor structures in which the floating gate used to store charge upon programming of the cell is formed from a single layer of polysilicon. These single-poly flash EEPROMs are particularly well suited for use in applications requiring embedded, low cost, medium density arrays of non-volatile memory cells, such as parameter, protocol, code and data storage for processors and other types of integrated circuits.
Examples of single-poly flash EEPROM memory cells known in the art are described in U.S. Pat. No. 6,191,980, issued Feb. 20, 2001 in the name of inventors P. J. Kelley et al. and entitled “Single-Poly Non-Volatile Memory Cell Having Low-Capacitance Erase Gate,” R. J. McPartland et al., “SRAM Embedded Memory with Low Cost, FLASH EEPROM-Switch-Controlled Redundancy,” Proceedings of the IEEE Custom Integrated Circuits Conference, Orlando, Fla., May 21-24, 2000, pp. 287-289, and R. J. McPartland and R. Singh, “1.25 Volt, Low Cost, Embedded FLASH Memory for Low Density Applications,” Proceedings of the 2000 Symposium on VLSI Circuits, Honolulu, Hawaii, Jun. 15-17, 2000, pp. 158-161, all of which are incorporated by reference herein.
FIG. 1
shows a schematic diagram of a single-poly flash EEPROM memory cell
100
of the type described in the above-cited U.S. Pat. No. 6,191,980. The memory cell
100
includes a control device M
1
in the form of a control gate capacitor, a switch device M
2
, and an erase device M
3
. M
1
and M
3
are implemented as P-type metal oxide semiconductor (PMOS) devices, and M
2
is implemented as an N-type MOS (NMOS) device. The control device M
1
, switch device M
2
and erase device M
3
all share a common polysilicon floating gate
102
designed to retain charge after the cell is written, i.e., programmed.
Programming in the memory cell
100
is by hot electron injection and erasure is by Fowler-Nordheim (F-N) tunneling. In operation, the cell is written or programmed by applying a voltage of about 5 volts to control gate
104
while drain terminal
108
of M
2
is about 5 volts and erase gate
106
and source terminal
10
of M
2
are held at about 0 volts, and the cell is erased by applying a voltage of about 10 volts to erase gate
106
while control gate
104
and terminals
108
and
110
are held to about 0 volts.
The object of an erase operation is to raise the potential of the floating gate
102
such that when the floating gate is coupled to the control gate
104
during a subsequent read operation, the potential of the floating gate will be above the threshold of the switch device M
2
and M
2
will thereby be conductive. Tunneling of electrons from the floating gate
102
through the gate oxide layer of device M
3
associated therewith to source/drain and N-well regions of device M
3
raises the potential of the floating gate. In a program operation, the potential of the floating gate
102
is lowered by the above-noted hot electron injection such that when the floating gate is coupled to the control gate
104
during a subsequent read operation, the potential of the floating gate will be below the threshold of the switch device M
2
and M
2
will thereby be non-conductive.
FIG. 2
shows a topological view of the memory cell
100
. The device
100
includes N-well regions
120
and
122
formed in a P-type substrate. Devices M
1
and M
3
are formed in the N-well regions
120
and
122
, respectively, while device M
2
is formed in an N-type source-drain implant region
124
. P-type source-drain implant regions
126
and
128
are formed in the respective N-well regions
120
and
122
. Thin oxide or “thinox” regions
130
and
132
are associated with the respective devices M
1
and M
2
, while thinox source/drain contact regions
134
and
136
are associated with the device M
3
. An additional thinox region
137
is present between the regions
134
and
136
. Windows
131
-
1
and
131
-
2
are formed in the thinox region
130
, and similar windows are formed in the thinox regions
132
and
134
. Elements
140
and
142
associated with the respective N-well regions
120
and
122
are N-well ties each having a window formed therein. Element
144
is a P-well tie associated with the P-type substrate.
FIGS. 3A and 3B
show respective topological and side sectional views of the erase device M
3
in the conventional memory cell
100
. The
FIG. 3B
sectional view is taken along the line B—B′ shown in FIG.
3
A. It can be seen from
FIG. 3A
that the floating gate
102
overlies the thinox region
137
. The N-well tie
142
of
FIG. 3A
is formned in a P-type substrate
160
and corresponds to a region
162
in the N-well
122
. Source/drain contact regions
134
and
136
correspond to source/drain regions
164
and
166
in the N-well
122
. As is apparent from the schematic diagram of
FIG. 1
, both the source/drain regions
164
,
166
and the N-well tie region
162
are electrically connected together to form one terminal (i.e., erase gate
106
) of the erase device M
3
. The other terminal of the erase device M
3
is the floating gate
102
. The erase operation in the memory cell
100
involves tunneling of electrons from the floating gate
102
to the source/drain and N-well tie regions, via the above-noted F-N tunneling effect.
A potential drawback of the memory cell
100
is the amount of circuit area required to implement the erase device M
3
. More particularly, the erase device M
3
of the memory cell
100
as illustrated in
FIGS. 3A and 3B
includes the N-well tie region
162
and two source/drain regions
164
,
166
, which collectively occupy a substantial amount of area within the memory cell
100
. In addition, when multiple memory cells of this type are combined into a memory cell array, the erase device M
3
is replicated in fail for each of the memory cells, further increasing the area requirements. For example, an array of eight non-volatile memory cells would conventionally require eight separate erase devices having a total of sixteen source/drain contacts and eight N-well tie contacts. However, in order to minimize fabrication costs for the corresponding memory device, it is desirable to reduce the memory cell area. A need therefore exists in the art for a non-volatile memory cell and associated cell array having an erase device structure which requires less area than the conventional arrangements previously described.
SUMMARY OF THE INVENTION
The present invention overcomes the above-described drawback of the prior art by providing a non-volatile memory device in which an array of memory cells share an erase device.
In accordance with one aspect of the invention, a non-volatile memory device includes an erase device that is shared among an array of memory cells. Each of the memory cells includes a control device coupled to a switch device via a common floating gate. Each of at least a subset of the memory cells further includes a portion of the shared erase device, the portion of the shared erase device associated with a given one of the memory cells being coupled to the switch device of that cell via the floating gate of that cell. The shared erase device is utilizable in performing an erase operation for each of the memory cells associated therewith.
In an illustrative embodiment of the invention, a non-volatile memory cell array includes eight memory cells, and

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