Non-volatile memory cell array and logic

Details Non-volatile memory cell array and logic Non-volatile memory cell array and logic

2008-07-07

2010-12-07

Sefer, A. (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Lateral bipolar transistor structure

C257S564000, C257SE21610, C257SE21613

Reexamination Certificate

active

07847374

ABSTRACT:
A semiconductor device comprising a memory region including one or more transistor string arrays, a logic region including one or more logic transistors and an isolation region for isolating the logic transistors. The string array includes a plurality, T, of bipolar junction transistors. The string array includes a common collector region for the T bipolar junction transistors, a common base region for the T bipolar junction transistors, a plurality of emitters, one emitter for each of the T bipolar junction transistors, a number, B, of base contacts for the T bipolar junction transistors where the base contacts electrically couple the common base region and where the number of base contacts, B, is less than the number of transistors, T.

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patent: 2003/0030084 (2003-02-01), Moise et al.
patent: 2006/0049392 (2006-03-01), Pellizzer et al.

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