Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2008-07-15
2008-07-15
Le, Vu A (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185160
Reexamination Certificate
active
11785285
ABSTRACT:
A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.
REFERENCES:
patent: 4017888 (1977-04-01), Christie et al.
patent: 4151021 (1979-04-01), McElroy
patent: 4173766 (1979-11-01), Hayes
patent: 4173791 (1979-11-01), Bell
patent: 4257832 (1981-03-01), Schwabe et al.
patent: 4306353 (1981-12-01), Jacobs
patent: 4342149 (1982-08-01), Jacobs
patent: 4360900 (1982-11-01), Bate
patent: 4382827 (1983-05-01), Romano-Moran et al.
patent: 4471373 (1984-09-01), Simizu et al.
patent: 4521796 (1985-06-01), Rajkanen et al.
patent: 4527257 (1985-07-01), Cricchi
patent: 4667217 (1987-05-01), Janning
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 4742492 (1988-05-01), Smayling et al.
patent: 4743564 (1988-05-01), Sato et al.
patent: 4754314 (1988-06-01), Scott et al.
patent: 4769340 (1988-09-01), Chang et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5104819 (1992-04-01), Freiberger et al.
patent: 5168334 (1992-12-01), Mitchell et al.
patent: 5268590 (1993-12-01), Pfiester et al.
patent: 5311049 (1994-05-01), Tsuruta
patent: 5324675 (1994-06-01), Hayabuchi
patent: 5371702 (1994-12-01), Nakai et al.
patent: 5418176 (1995-05-01), Yang et al.
patent: 5424567 (1995-06-01), Chen
patent: 5426605 (1995-06-01), Van Berkel et al.
patent: 5436481 (1995-07-01), Egawa et al.
patent: 5511020 (1996-04-01), Hu et al.
patent: 5578855 (1996-11-01), Gaffur et al.
patent: 5621687 (1997-04-01), Doller
patent: 5629224 (1997-05-01), Rostoker et al.
patent: 5633202 (1997-05-01), Brigham et al.
patent: 5825686 (1998-10-01), Schmitt-Landsiedel et al.
Paulsen, R.E., et al “Observation of near interface oxide traps with charge pumping technique”, IEEE Electron Device Letters, vol. 13, No. 12, Dec. 1992.
Pan, Cheng-Sheng, et al “A Scaling Methodology for Oxide-Nitride-Oxide Interpoly Dielectric for EPROM Applications”, IEEE Transactions on Electron Devices, vol. 17, No. 6, Jun. 1990.
Eitan Boaz
Maayan Eduardo
EMPK & Shiloh, LLP
Le Vu A
Saifun Semiconductors Ltd.
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