Non-volatile memory cell and array using substrate current

Communications: electrical – Digital comparator systems

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307238, 357 23, G11C 1140, G11C 700

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active

039927016

ABSTRACT:
A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current. The cell includes spaced source and drain regions, a gate dielectric layer capable of trapping a charge, a substrate contact electrode; a means to induce a trapped charge into the gate dielectric layer, including a means to apply a voltage larger than the threshold voltage to the gate electrode to form an inversion layer, and a means to apply a voltage to the drain electrode causing channel current to flow; a means to remove the trapped charge, including a means to apply a voltage equal to or exceeding the avalanche voltage to the drain to cause avalanching; a means to determine the presence or absence of a charge in the gate dielectric including a means to apply a voltage to the gate which is larger than the threshold voltage and a voltage to the drain that is significantly less than the avalanche voltage, and a means to determine the substrate current.

REFERENCES:
patent: 3508211 (1970-04-01), Wegener
patent: 3549911 (1970-12-01), Scott
patent: 3646527 (1972-02-01), Wada et al.
patent: 3836992 (1974-09-01), Abbas et al.
patent: 3846768 (1974-11-01), Krick
Ragonese et al., Circuit and System Aspects of Variable Threshold FET Arrays, pp. 134-135, 1970, IEEE International Convention Digest, pp. 23-26, Mar., 1970.
Dill, et al., A New MNOS Charge Storage Effect, Solid-State Electronics, Pergamon Press, 1969, vol. 12, pp. 981-987.
Chiu, Programmable Read-Only Memory Stack Gate FET, IBM Technical Disclosure Bulletin, vol. 14, No. 11, 4/72, p. 3356.
Abbas, Substrate Current-A Device and Process Monitor, reprint from 1974 "IEDM Technical Digest," pp. 404-407.

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