Non-volatile memory cell

Details Non-volatile memory cell Non-volatile memory cell

2003-04-04

2004-11-23

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Tunneling through region of reduced conductivity

C257S315000

Reexamination Certificate

active

06822254

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory cells, and in particular, to a non-volatile memory cell and a method of manufacturing a non-volatile memory cell.
BACKGROUND OF THE INVENTION
Non-volatile memory is required for both field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). An FPGA utilizes a dedicated non-volatile memory chip for storing the bit streams required to program the FPGA. A CPLD integrates on-chip logic cores, non-volatile memory and high-voltage components to erase/program the memory. In current CPLD products, the memory cells and high-voltage components can consume up to 40% of the device silicon. Therefore, significant savings in silicon expense can be realized by reducing the memory cell size and area required by high voltage components. In integrated circuit manufacturing, even small cost reductions can open significant markets where a product is uncompetitive due to cost.
While some conventional CPLDs employ non-volatile electronically erasable (EE)-flash cells, which are small, EE-flash cells have the disadvantage of requiring both negative and positive high-voltage for program/erase. A memory cell requiring both positive and negative high voltages requires two separate charge pumps with regulation and control. This requirement increases the silicon cost for memory and support circuitry as compared to approaches with comparable cell size but requiring only a single high voltage. Further, fabricating these EE-flash cells requires one more processing step than the number of processing steps required for EE-cells requiring a single high voltage.
Similarly, some conventional memory cells, although only requiring a single, positive high voltage, have 3 transistors (i.e. 3-T memory cells). Because a 3-T memory cell has both an access transistor gate and a program/erase transistor gate, it is relatively large (~15 &mgr;m
2
). To save area, the conventional memory cell shown in
FIGS. 1-4
utilizes three transistors with the access and program/erase transistor gates tied together to significantly reduce the size compared to other conventional 3-T memory cells. However, many advantages of the 3-T cell are lost when the gates are tied together.
Other memory cells have only two transistors (i.e. 2-T memory cells). Although 2-T memory cells are smaller than 3-T memory cells, the switching between high-voltage for program/erase and low logic-level voltage for reading the cell must be done outside the memory cell array. However, switching large groups of cells outside the array rather than in each cell saves significant die area.
In addition to reducing the number of transistors, there are different approaches to defining a tunnel oxide etch for a memory cell which affect the size of the memory cell. By implementing a large area tunnel oxide etch, the designer achieves significantly easier alignment, easier etch control and smaller cell-size. Having less stringent alignment requirements yields less expensive masks and easier processing. However, the large tunnel oxide etch can produce a dielectric with high leakage at the metallurgical junction between the active area (also commonly called the diffusion area) and the silicon field oxide or the edge of the polysilicon. Because high leakage is detrimental to a memory cell, the tunnel oxide etch patterned area can be moved inside the active area (i.e. small tunnel oxide etch) to avoid the high-leakage region above the metallurgical junction. However, when using a small tunnel oxide etch, a smaller area opening must be patterned, and a smaller area opening is more subject to misalignment errors. Further, the cell area must be made larger to accommodate the square tunnel window inside the active area while still providing reasonable alignment tolerances.
Accordingly, there is a need for a non-volatile memory cell having a smaller area and/or improved properties, and a method of manufacturing the non-volatile memory cell.
SUMMARY OF THE INVENTION
A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the floating gate transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor.
A method of manufacturing a non-volatile memory cell incorporated in an integrated circuit is also disclosed. The method comprises the steps of creating a two transistor memory cell; creating a coupling capacitor associated with a gate of a floating gate transistor of the two transistor memory cell; and etching the coupling capacitor to minimize the capacitance of the gate to source capacitance of the floating gate transistor and tunneling capacitor capacitance.


REFERENCES:
patent: 4408303 (1983-10-01), Guterman et al.
patent: 5248624 (1993-09-01), Icel et al.
patent: 5587945 (1996-12-01), Lin et al.
patent: 5914514 (1999-06-01), Dejenfelt et al.
patent: 6265266 (2001-07-01), Dejenfelt et al.

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