Non-volatile memory cell

Details Non-volatile memory cell Non-volatile memory cell

2005-12-13

2005-12-13

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185260

Reexamination Certificate

active

06975545

ABSTRACT:
A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well and between the first doped region and the second doped region from among the three P-type doped regions. The first gate is formed on the first stacked dielectric layer. The second stacked dielectric layer is formed on the N-type well and between the second doped region and the third doped region from among the three P-type doped regions. The second gate is formed on the second stacked dielectric layer.

REFERENCES:
patent: 6750102 (2004-06-01), Lancaster
patent: 6831863 (2004-12-01), Yi et al.
patent: 6838345 (2005-01-01), Chang
patent: 6861701 (2005-03-01), Williams et al.
patent: 6870765 (2005-03-01), Fujiwara
patent: 2003/0227049 (2003-12-01), Sakakibere
patent: 2004/0005764 (2004-01-01), Wu et al.

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