Non-volatile memory array with equalized bit line potentials

Details Non-volatile memory array with equalized bit line potentials Non-volatile memory array with equalized bit line potentials

2001-09-25

2003-03-11

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090, C365S230060

Reexamination Certificate

active

06532176

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to non-volatile memory structures, and more particularly, to methods and apparatus for charging, discharging or equalizing potentials in a non-volatile memory array to provide conditions for sensing non-volatile memory cells in the array.
DISCUSSION OF RELATED ART
Non-volatile memory arrays include a plurality of non-volatile memory (NVM) cells arranged in rows and columns. In general, single-transistor n-channel NVM cells operate as follows. During an erase operation, electrons are removed from a floating gate of the NVM cell, thereby lowering the threshold voltage of the NVM cell. During a program operation, electrons are inserted into the floating gate of the NVM cell, thereby raising the threshold voltage of the NVM cell. Thus, during program and erase operations, the threshold voltages of selected NVM cells are changed. During a read operation, read voltages are applied to selected NVM cells. In response, read currents flow through these selected NVM cells. The magnitudes of the read currents are dependent upon the threshold voltages of the selected NVM cells.
FIG. 1
is a flow diagram of a typical read cycle algorithm, which includes Steps
101
-
108
. After starting the read cycle (Step
101
), an address corresponding with the selected NVM cells is decoded (Step
102
). In response, a first read voltage is applied to a selected row, or word line (Step
103
), and a second read voltage is applied to selected columns, or bit lines (Step
104
). The resulting read currents are sensed by corresponding sense amplifiers (Step
105
) to determine whether the corresponding NVM cells have programmed or erased states (i.e., high or low threshold voltages). The sensed data values are then provided as output data values (Step
106
), thereby completing the read operation (Step
107
). Note that after the read currents have been sensed, the selected bit lines are prepared for the next memory cycle (Step
108
). Typically, this involves pre-charging or equalizing the selected bit lines to a predetermined voltage.
FIG. 2
is a circuit diagram of a portion of a conventional non-volatile memory array
200
, which includes NVM cells
201
-
204
, word line
210
and bit lines BL
A
, BL
B
and BL
C
. Bit lines are modeled using resistors
221
-
226
and capacitors
231
-
233
.
During a first read cycle, NVM cell
202
is selected (Steps
101
-
102
). Thus, a first read voltage is applied to word line
210
during the first read cycle (Step
103
). In addition, voltage source
241
is coupled to BL
A
during the first read cycle, thereby applying the second read voltage V
X
to bit line BL
A
(Step
104
). Sense amplifier
251
is coupled to bit line BL
B
during the first read cycle (Step
104
). Under these conditions, a first read current I
AB
flows through NVM cell
202
. Sense amplifier
251
senses the magnitude of this read current I
AB
to determine the state of NVM cell
202
(Step
105
). In the described example, NVM cell
202
is programmed to a high threshold voltage, such that sense amplifier
251
identifies a logic low read current. A data amplifier (not shown) coupled to sense amplifier
251
provides the low data output signal (Step
106
). Bit line BL
B
, which becomes charged during the read operation, is discharged after the data value has been sensed (Step
108
). Normally, the voltage on word line
210
remains activated at the first read voltage while bit line BL
B
is being discharged. As a result, bit line BL
A
is discharged to an acceptable level through NVM cell
202
.
However, if non-volatile memory array
200
is operated in an asynchronous manner, it is possible for a second read cycle to interrupt the first read cycle. In this case, the second read cycle will cause the voltage on word line
210
to be de-activated low while bit line BL
B
is being discharged. As a result, a relatively large charge Q
X
is stored (trapped) on bit line BL
A
(i.e., capacitor
231
).
In the described example, NVM cell
203
, which is programmed to a high threshold voltage, is selected during the second read cycle. Thus, the first read voltage is applied to word line
210
during the second read cycle. In addition, voltage source
242
is coupled to bit line BL
C
during the second read cycle, thereby applying the read voltage V
Y
, to bit line BL
C
(Step
104
). Sense amplifier
251
is coupled to bit line BL
B
during the second read cycle (Step
104
). Under these conditions, a small read current I
CB
flows through NVM cell
203
to sense amplifier
251
.
In addition, because bit line BL
A
was not previously discharged, sense amplifier
251
receives a small current I
AB
, associated with the charge Q
X
stored on bit line BL
A
. As a result, the actual read current on bit line BL
B
is equal to the current through NVM cell
203
(from read voltage V
Y
), plus the current through NVM cell
202
(from trapped charge Q
X
). Thus, the actual read current provided to sense amplifier
251
on bit line BL
B
is about twice as high as the desired read current I
CB
.
Sense amplifier
251
senses the magnitude of the actual read current to determine the state of NVM cell
203
(Step
105
). In the described example, it is possible that sense amplifier
251
will erroneously determine that NVM cell
203
has an erased state (i.e., a low threshold voltage) in response to the relatively high actual read current.
Note that the address of the second read cycle can be selected randomly, so it is not possible to predict which bit lines must be discharged prior to the second read cycle. Thus, conventional non-volatile memory systems require that all bit lines involved in a read operation be discharged before the next read cycle begins. As a result, the operating speed of these non-volatile memory systems is reduced, and the operating power of these non-volatile memory systems is increased. Moreover, conventional non-volatile memory systems are typically divided into several blocks, whereby each block must be activated for each discharge operation, thereby resulting in very high power consumption.
It would therefore be desirable to have a memory system that overcomes the above-described deficiencies of conventional non-volatile memory systems.
SUMMARY
Accordingly, the present invention provides a non-volatile memory (NVM) system that includes an array of NVM cells arranged in rows and columns, wherein each column of NVM cells shares a common bit line with an adjacent column of NVM cells. One row of the array forms a dedicated row of equalization NVM cells. Each of the equalization NVM cells is initially erased, such that these equalization NVM cells exhibit a low threshold voltage during normal operation of the array. After the equalization NVM cells have been erased, these cells are not programmed, erased, or read during normal operation of the array.
An equalization control circuit is configured to detect the beginning of each read cycle. In one embodiment, the equalization control circuit receives an access enable signal and a read/write indicator signal, which are both activated at the beginning of each read cycle. Upon detecting the beginning of a read cycle, the equalization control circuit activates an equalization control signal. The activated equalization control signal is applied to the word line of the row of equalization NVM cells, thereby turning on these equalization NVM cells. The turned on equalization NVM cells electrically connect the bit lines of the array, thereby causing the bit lines to discharge (i.e., equalize) at the beginning of each read cycle. The equalization control signal is de-activated after the bit lines have had an opportunity to discharge, but prior to a bit line sensing period of the read cycle.
Because the bit lines are discharged at the beginning of each read cycle, minimal charges remain on the bit lines during the sensing period. As a result, bit line charges will not result in erroneous read results, even if a first read cycle is interrupted by a second read cycle.
The present invention will be

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