Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-04-19
2003-02-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185090, C365S104000
Reexamination Certificate
active
06522582
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application relates to
1. U.S. patent application Ser. No. 09/552,285 entitled “Redundancy Scheme to Improve Programming Yield for Non-Volatile Memory Using Gate Breakdown Structure in Standard Sub 0.25 Micron CMOS Process” commonly owned and filed concurrently with the present application.
2. U.S. patent application Ser. No. 09/552,625 entitled “Improved Array Arrangement for Non-Volatile Memory Using Gate Breakdown Structure in Standard Sub 0.25 Micron CMOS Process” commonly owned and filed concurrently with the present application.
3. U.S. patent application Ser. No. 09/524,971 entitled “Intellectual Property Protection in a Programmable Logic Device” commonly owned and filed Mar. 14, 2000. These related applications are incorporated herein by reference.
TECHNICAL FIELD
This invention relates to integrated circuits, and more particularly to memory architectures including various cell structures and charge pumps for use in non-volatile memory arrays.
BACKGROUND OF THE INVENTION
Many integrated circuits now in use are fabricated in what is called CMOS (complimentary metal oxide semiconductor) technology, which forms both PMOS and NMOS transistors in a semiconductor substrate. The term “semiconductor substrate” is defined to mean any construction comprising semiconductor material, including, but not limited to, bulk semiconductor materials such as a semiconductor wafer (either alone or in assemblies comprising other material they are on), and semiconductor material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
One of the main objectives of integrated circuit technology is to minimize transistor size. Typically, transistors are described in terms of their minimum feature dimension. Current technology provides a minimum feature size of 0.35 micron or less. The minimum feature size, which is also referred to as a “line width”, refers to the minimum width of a transistor feature such as the gate width, or the separation between source and drain diffusion regions. Typically, 0.35-micron technology is used to form CMOS transistors having gate oxide thicknesses of around 70 Angstrom. A 0.18-micron technology is used to form CMOS transistors having a gate oxide thickness of around 35-40 Angstrom. A 0.15-micron technology is used to form CMOS transistors having a gate oxide thickness of around 25-30 Angstrom. The gate “oxide” is typically an oxide dielectric layer that is interposed between the conducting gate electrode, which is typically a polycrystalline silicon structure formed overlying the principle surface of a substrate in which the integrated circuit is formed, and the underlying substrate which typically is the channel portion of the transistor extending between the source and the drain regions. Transistors formed using the 0.35-micron technology typically operate at a voltage of 3.3 Volts. Transistors formed using the 0.18-micron technology typically operate at a voltage of 1.8 Volts. Greater voltages are likely to destroy the transistor by rupturing the gate oxide.
In the field of data storage, there are two main types of storage elements. The first type of storage element is a volatile storage element such as typically used in DRAM (dynamic random access memory) or SRAM (static random access memory) in which the information stored in a particular storage element is lost when power is removed from the circuit. The second type of storage element is a non-volatile storage element in which the information is preserved even if power is removed. Typically, the types of elements used to provide non-volatile storage are substantially different from those used in ordinary logic circuitry or in volatile storage, thereby requiring different fabrication techniques. It has heretofore not been possible to include non-volatile storage on an integrated circuit chip formed exclusively using standard CMOS processes.
SUMMARY
Memory architectures including various cell structures for use in non-volatile memory arrays and methods of programming memory cells are described. In the described embodiments, the cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures are fabricated using 0.18 micron or 0.15 micron standard CMOS processes. This enables the transistors that are utilized for both the storage transistors and the pass transistors (I/O transistors) to be formed using standard CMOS processing techniques.
Advantageously, the cell structures that are formed can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
In particular embodiments, the cell structures are fabricated utilizing standard 0.18 micron or 0.15 micron CMOS processes. In these embodiments, memory cells are fabricated comprising storage structures, including transistors, having different gate breakdown characteristics, e.g. as impacted by the thicknesses of their gate dielectric layers. The memory cells are programmed by taking advantage of the different gate breakdown characteristics of the different memory cells.
In one embodiment, a method of programming a non-volatile memory cell comprises providing a storage transistor over a substrate. The storage transistor comprises a gate and a pair of source/drain regions that are formed within the substrate. A programming voltage is applied to the storage transistor sufficient to form a conductive path between the gate and one of the pair of source/drain regions.
In another embodiment, a method of programming a non-volatile memory cell comprises providing a storage structure over a substrate. The storage structure comprises a gate at least a portion of which is disposed proximate a region of the substrate. The gate and the substrate region comprise the same type material. A programming voltage is applied to the storage structure sufficient to form a conductive path between the gate and the substrate region.
In yet another embodiment, a non-volatile memory cell comprises a substrate and a low voltage CMOS storage transistor supported by the substrate. The storage transistor comprises a gate, a gate dielectric, and a pair of source/drain regions received within the substrate. The memory cell is configured for programming by rupturing the gate dielectric of the storage transistor. The memory cell also comprises a high voltage p-channel transistor having a pair of source/drain regions. One of the pair of source/drain regions of the p-channel transistor is coupled with one of the pair of source/drain regions of the CMOS storage transistor. The storage transistor is configured for programming through the p-channel transistor.
In yet another embodiment, a non-volatile memory cell comprises a substrate and a low voltage p-channel storage transistor supported by the substrate. The storage transistor comprises a gate, a gate dielectric, and a pair of source/drain regions received within a well in the substrate. The memory cell is configured for programming by rupturing the gate dielectric of the storage transistor. The memory cell also comprises a high voltage p-channel transistor having a pair of source/drain regions. One of the pair of source/drain regions of the high voltage p-channel transistor is coupled with the gate of the low voltage p-channel storage transistor. The storage transistor is configured for programming through the high voltage p-channel transistor. In a further embodiment, a field programmable gate array (FPGA) comprises a substrate, a plurality of word lines supported by the substrate, a p
Bankras Radko G.
Gitlin Daniel
Hart Michael J.
Jeong Jongheon
Karp James
Le Thong
Nelms David
Wallace, Esq. T. Lester
Xilinx , Inc.
Young Edel M.
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