Non-volatile memory architecture to improve read performance

Details Non-volatile memory architecture to improve read performance Non-volatile memory architecture to improve read performance

2006-03-07

2006-03-07

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S189020, C365S230030

Reexamination Certificate

active

07009880

ABSTRACT:
A memory cell array is physically divided into an even number of sectors, with each pair of sectors sharing read circuitry. The outputs of the shared read circuitry are commonly connected to form data lines spanning the height of the array, which are input to global sense amplifiers. A two-stage sensing scheme is employed, with first stage and global sense amplifiers. The driving capability of the first stage sense amplifier can be used to decrease the time to charge or discharge the data lines, which reduces the total signal development time and consequently improves read performance. Granularity of the array can be adjusted by dividing groups and sub-groups of memory cells within a sector accordingly. In a read operation, the bit line in the opposite sector at the same column location is used as reference bit line, which greatly improves matching of bit line loading for the sensing.

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